| Mentor, a Siemens Business, Hosts Annual EDA Forum
| Sawiki VP: “ML Growth Drives Changes in EDA Tools”
| HLS, increasing the speed and accuracy of semiconductor design verification

Advances in machine learning, deep learning, and artificial intelligence are also having a significant impact on the semiconductor design market.

Mentor, a Siemens business, held the 'Mentor Forum 2019', an annual EDA (Electronic Design Automation) event, on the 3rd floor of the Lotte World Hotel in Jamsil, Seoul on August 30th.

Joseph Sawicki, Senior Vice President of Mentor IC EDA, who visited Korea for the forum, predicted that the semiconductor design industry will continue to grow as the development of AI-based domain-specific architecture products increases in his keynote speech titled “The Impact of AI on Semiconductors and EDA.”

“Venture capital investment in semiconductor design based on machine learning (ML) is increasing,” said Vice President Sawicki. “As the ML market grows, EDA tools are also gaining many opportunities.”He mentioned AI and ML fields as specialized architectures. And he mentioned 'HLS (High Level Synthesis)' as an example of a new design technology that can create AI/ML accelerators optimized for edge applications.

HLS is a technology that can increase the speed and accuracy of semiconductor design verification by directly supporting high-level programming languages such as C and C++, and enables architectural exploration that is important to ML, especially around memory. It also enables high-performance FPGA demonstrations and can deliver optimal power, performance, and area for ASIC IP. As an example of utilizing this HLS, NVIDIA's Tegra X1 - DNN (Deep Neural Networks) for self-driving cars was introduced.

As the ML market grows, the areas of EDA utilization are also expanding.

In the case of OPC (Optical Proximity Correction), which can predict process results through a model, the use of ML made it possible to achieve results within a 1 nm error range with an execution time three times faster.

LFD (Litho Friendly Design) improved the prediction speed of yield-limiting factors by 10 times by utilizing ML, and was able to discover new yield-limiting factors that were not previously discovered.

DDYA (Diagnosis Driven Yield Analysis) for yield improvement can also be achieved through ML. Noise removal can shorten the time to identify the cause of yield loss and improve yield by identifying hidden yield-limiting factors.

ML bias-aware design and characterization can also be used for hundreds of thousands of simulations required to verify repetitively used components such as memory blocks and standard cells. This can not only speed up library characterization and verification, but also improve library quality and improve power, performance, area (PPA).

In order to verify that AI/ML/DL (Deep Leaning) design algorithms are optimized for the actual SoC environment, emulation that can simultaneously operate and accelerate hardware and software is essential. Mentor's 'Emulator Veloce' can also emulate data such as sensors through a virtual environment, further accelerating verification.

“Smart systems are driving intelligence everywhere, and specialized IC design based on AI/ML is also accelerating,” said Vice President Sawicki. “Implementing cutting-edge intelligence requires IC innovation combined with expertise in system design.”

“Mentor, a Siemens business, will actively support customers who need an EDA partner with expertise ranging from smart ICs to systems, factories, and cities,” he said.