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ETRI Realizes 'Capacitor-Free DRAM' Using Oxide Semiconductors for Displays

Google 우선 소스 기사입력2026.04.14 11:36



Presenting an alternative to reduce the miniaturization burden of the existing 1T1C structure
Data retention 1,000 seconds · Memory Windows improved 13-fold
The Electronics and Telecommunications Research Institute (ETRI) has implemented a 2T0C DRAM structure that stores data without capacitors by utilizing oxide semiconductors for displays. This is significant in that it addresses the capacitor problem, which has been pointed out as a limitation in the process of high-density DRAM integration, through a new structure.

The results of this study were published in the online edition of the international academic journal Advanced Science on March 3, 2026, and ETRI disclosed the details on April 14. The research focused on implementing a storage structure different from existing silicon DRAM, based on oxide semiconductor thin-film transistors.

Currently, commercial DRAMs primarily use a 1T1C structure combining one transistor and one capacitor. However, as integration density increases, it becomes difficult to stably form capacitors, and process complexity and power burden also increase. For this reason, a structure without capacitors has been consistently reviewed, but data retention performance and operational stability remained challenges to be solved.

ETRI researchers used Al:ITZO, an indium-tin-zinc oxide with added aluminum, as a transistor material and controlled internal defects using an N2O plasma process. In addition, they adjusted the channel ratio of the read transistors to design the device so that stored charge does not easily disappear. As a result, the data retention time increased to over 1,000 seconds, and the memory window for distinguishing data improved by approximately 13 times.

This achievement can be viewed as a case demonstrating that oxide semiconductor technology for displays can be extended into the realm of memory devices. While it does not immediately signify commercialization, it is interpreted as suggesting a direction for next-generation low-power, high-density memory research by showing the extent to which a structure with reduced capacitor dependency has secured potential for actual memory applications.