As the demand for CXL-based memory expansion grows alongside the proliferation of AI workloads, a domestic company presents technical evidence at the academic stage demonstrating that latency can be maintained at a level similar to existing direct connection methods, even during large-scale connections via switches.

Panesia (CEO Jung Myung-soo) announced that it will present its next-generation CXL (Compute Express Link) controller and fabric switch technology equipped with it at the ISCA 2026 Industry Session, an international conference on computer architecture to be held in Raleigh, USA, on June 29.

Meta's CXL-related paper is also scheduled to be presented in the same session.

The next-generation CXL controller proposed by Panesia reduces latency by applying a layered buffer sharing structure to decrease synchronization overhead.

Existing CXL controllers, developed based on PCIe (PCI Express), had a characteristic of structural delay during internal data transmission due to the independent management of layered buffers.

Panesia explained that it improved this by applying additional layered optimization in parallel.

The core of switch technology is support for port-based routing (PBR).
Unlike the existing Layered Routing (HBR), which could only connect devices in a tree structure, PBR transmits data based on port IDs, allowing for the flexible configuration of connections between devices.

Panesia stated that its next-generation CXL fabric switch supports both PBR and HBR, and maintained stable performance even in an environment with 64 connected servers in a paper evaluation.

The existing method is known to limit the number of connectable servers to a few.

CEO Jeong Myeong-su explained, “Until now, the method of directly connecting the Multi-Head Device (MHD) to the CPU has been primarily used due to the perception that adding switches makes it difficult to meet latency requirements,” adding, “This research demonstrates that this is not an inherent limitation of CXL, but rather a characteristic of the early-stage implementation.”

Panesia announced that it has advanced the technology covered in this paper to secure a pre-distribution chip for the 'PCIe 6.4-CXL 3.2 Fusion Switch' and has also completed the commercialization of the 'PCIe 7.0-CXL 4.0 Combo IP' with the latest standards.