RP235x Ecosystem

Cortex-M33/RISC-V dual option, TrustZone, OTP, HSTX, enhanced PIO…

Extending the versatility of the RP2040 to mass production sites

Raspberry Pi has unveiled its next-generation microcontroller (MCU) series, the RP235x, highlighting its security, high-speed I/O, and display drive capabilities. Lee Min-jong, deputy manager of Raspberry Pi technical support at Insem, said at a recent seminar, “The RP235x is an MCU aimed at mass production sites, beyond hobbyists and education.” He added, “While maintaining the accessibility of the RP2040, it offers a leap forward in security, interface, and memory expandability.”

The RP235x adopts a dual processor structure, allowing you to choose between Arm Cortex-M33 (up to 150MHz) and RISC-V Hazard3. In particular, when choosing M33, the key point is that it can separate the secure area and the general area by utilizing Arm TrustZone, protecting sensitive data and firmware at the hardware level.

The built-in memory consists of up to 520KB SRAM (10 banks) and 32KB boot ROM, and an 8KB OTP (one-time programmable) area can store the device's unique identifier and secure boot key.

External memory can be expanded up to 16 MB of flash and PSRAM via the QSPI interface, and code execution performance is enhanced through the Execute-In-Place (XIP) cache. This next-generation memory configuration takes into account the increasing code and resource demands of IoT, gateways, and small HMIs.

Vice President Lee emphasized, “We have created ‘security defaults’ by embedding TrustZone, OTP, SHA-256 accelerator, and random number generator (TRNG) into the chip as standard,” and “We can reduce the attack surface that is difficult to block with software policies alone with hardware.” The peripherals and I/O have been expanded compared to the RP2040. The RP235x provides three PIO (programmable I/O) blocks, and each block can operate four state machines, for a total of 12 in parallel.

PIO is a unique strength of the Raspberry Pi that improves real-time performance and power efficiency by processing non-standard protocols or special sensor interfaces without CPU intervention.

A new HSTX (High-Speed Serial Transmission) block has been added, enabling configurations of up to four lanes. Designed with display interfaces like MIPI DSI or LVDS in mind, it expands the potential for MCU-only graphics output in HMI, instrumentation, and educational systems that directly drive small displays. Standard peripherals are also provided.

It contains all the necessary configurations for embedded applications, including 24-channel PWM, 12-bit ADC (up to 8 channels), 2×UART·SPI·I²C, and USB OTG (built-in PHY, 4KB dedicated SRAM).

The chip's internal connections are designed with an AHB5 crossbar-based bus fabric, allowing dual cores and DMA to access memory and peripherals in parallel. Stability is ensured by two PLLs, segmented power domains, and a global exclusivity monitor (which ensures exclusive access to multicore shared resources).

The operating voltage is 1.8 to 3.6 V and the operating temperature is -40 to 85°C, making it suitable for industrial and outdoor environments.

The package comes in two types, QFN60 and QFN80, with the A series (RP2350A and RP2354A) providing 30 GPIOs and the B series (RP2350B and RP2354B) providing 48 GPIOs. The RP2350A/B supports external flash only, while the RP2354A/B supports both 2MB internal flash and external flash.

The ADC channels are divided into four channels for the A series and eight channels for the B series. The RP2350A and RP2354A support pin-to-pin compatibility, allowing them to be interchanged on the same PCB depending on security and flash configuration. This reduces design risk and the burden of bill of materials (BOM) fluctuations.

The boot chain and memory map also reflect mass-production requirements. The boot ROM manages up to 16 areas based on the partition table and verifies image definitions and permissions to ensure their validity.

In addition to basic boot, it supports USB boot, allowing easy firmware update using UF2 files. The XIP area is reserved at 64MB, the lower 32MB is mapped to QSPI flash, and SRAM can be divided and placed according to purpose to optimize performance and power consumption.

Separating system and subsystem resets to selectively restart peripherals such as USB, PIO, PLL, and ADC also improves development and maintenance efficiency. The watchdog is designed to be segmented down to the power domain level, resetting only the necessary components in the event of a problem.

The development ecosystem is built around VS Code. Installing the Raspberry Pi "Pico" expansion pack provides drivers, examples, and a build environment, and supports both C/C++ and MicroPython.

SWD debugging and UART logging are easy to use with the Raspberry Pi 'Debug Probe', and flash downloads are simple thanks to the USB UF2 bootloader. Evaluation boards are available in the RP2350-based 'Pico 2' and the 'Pico 2 W' with added wireless communication, allowing projects to be converted to wireless/wired options with the same form factor and pinout.

“Developers can start right away on top of the familiar VS Code and Pico SDK and continue with a single ecosystem from prototype to mass production,” said Vice President Lee. “In Korea, Insem will provide integrated support for toolchains, boards, debugging equipment, and technical inquiry response.”

The application areas are wide, including IoT edge and industrial sensor nodes requiring security, small display-based HMIs, and measuring and educational equipment with many non-standard interfaces.

TrustZone and OTP-based secure boot, SHA-256 accelerator and TRNG are suitable for connected products that require authentication and key protection, and the PIO with 12 state machines flexibly responds to anomalous signals such as camera triggers, special LEDs, and legacy parallel buses.

HSTX targets customers who want to directly integrate low-cost panels into their GUIs. RP2040 users can seamlessly transition to higher-end models with expanded memory, security, and I/O capabilities while maintaining their code and development flow. Power management features such as power domains, low-power LDOs, and LP-OSCs support efficiency in battery-operated products.

Raspberry Pi has a two-tier structure that lowered the entry barrier with the RP2040 and then met 'production-level' requirements with the RP235x.

By maintaining the documentation, sample, and library assets accumulated by the education and maker communities, we have lowered the transition cost to commercial product development by adding three axes: security, display, and high-speed I/O.

The RP235x clearly conveys the message of "starting from one board to mass production" with its dual-core option, enhanced bus and memory, hardware security, and expanded peripherals. "The RP235x targets the balance between development speed, security, and real-time performance that are simultaneously required in the field," said Vice President Lee Min-jong. "We will refine the ecosystem so that domestic developers can quickly create prototypes with familiar tools and ensure mass production quality with the same toolchain."