Continuous-time delta-sigma ADC, no AAF design required
Switched capacitor DAC, etc. for jitter mitigation
Research using this method is being conducted domestically and internationally.


Analog-to-digital converters (ADCs) are essential circuits in sensors, IoT, audio, and communication systems, and demand for low-power, high-resolution ADCs has been increasing recently.

Current communication systems mainly use Nyquist ADC circuit structures such as Flash, Pipeline, and SAR ADC to convert high-speed analog signals into digital.

Recently, as higher resolution performance is required in high-speed circuits, the use of delta-sigma (ΔΣ) ADC structures is increasing.

Accordingly, Professor Seunghoon Lee of Sogang University's Department of Electronic Engineering announced 'High-reliability Continuous-Time Delta-Sigma ADC IP technology operating in a 20MHz signal band' in the weekly technology trend of the Information and Communications Technology Planning and Evaluation Institute (IITP) on the 3rd.

The continuous-time delta-sigma ADC architecture has the advantage of low power, which allows data-weighted AV (DWA)Professor Lee explained that chip size reduction and manufacturing cost reduction are possible through the elimination of the aliasing filter (AAF) effect. The continuous-time delta-sigma ADC structure does not require a separate related design because the anti-aliasing filter (AAF) effect is inherent in the circuit itself.

The continuous-time delta-sigma modulator designed by Professor Seung-Hoon Lee is suitable for high-speed wireless communication SoC and high-resolution sensor applications. It can handle up to 20MHz signal bandwidth and operates at 640MHz switching frequency with OSR (Oversampling Ratio) set to 16. It uses a third-order integrator and a 4-bit quantizer, and can achieve an SNR of 73dB, Professor Lee explained.

To compensate for the shortcomings of the continuous-time delta-sigma modulator, which is susceptible to clock jitter and excess loop delay, the professor explained that the first DAC uses the NRZ (Non-return to zero) method to reduce the impact of clock jitter. The second and third DACs are configured as digital differentiators to generate RZ (Return to zero) pulses, thereby compensating for excess loop delay.

Previously, a method was used to reduce the mismatch effect using DWA, but in this professor's design, the mismatch effect was reduced by using layout technology in the DAC part. This method can reduce the power consumption used in DWA.

Professor Lee Seung-hoon predicted that the mass production rate would not exceed 95% at the current stage of manually trimming the coefficients because the continuous-time delta-sigma modulator has a large coefficient change due to the process change rate, but he stated that this problem could be solved in the future by designing automatic trimming logic.

◇ Research is underway both domestically and internationally on open capacitors and capacitive feedforward structures to mitigate jitter effects.

According to the professor, research is currently underway in Korea to use a switched-capacitor DAC instead of a current-steering DAC to alleviate the effects of jitter, which is one of the problems of continuous-time delta-sigma ADCs. It is expected that by using this, the problem of performance degradation due to jitter can be solved without a PLL.

In addition, he added that when using a full feedback DAC structure, each DAC circuit is attached to each amplifier output terminal, which consumes a lot of power to increase the speed of the amplifier, and to solve this, a capacitive feedforward structure is mainly used.

In overseas countries, MASH is one of the methods to improve SNDR (Signal-to-noise and distortion ratio) performance while alleviating stability issues.(Multistage noise-shaping) Research on the structure is active, and linearity and matching problems are also being solved using the △VCO quantizer nonlinearity cancellation technique, and a technique called △DNSQ (Double noise-shaped quantizer) is also being studied, Professor Lee introduced.

Professor Seunghoon Lee recently published papers on continuous-time delta-sigma ADCs operating in signal bandwidths of tens to hundreds of MHz, and evaluated that they are also developing in terms of FoM (Figure of merit).