Kioxia-WD increases lateral cell array density
Implementing 6th generation 162-level vertical stacked memory
40% reduction in die area compared to 112-stage


Kioxia and Western Digital (WD) announced on the 24th that they have developed the 6th generation 162-layer 3D flash memory technology, which is the highest density ever achieved by either company.

The 6th generation 3D flash memory announced this time features an advanced architecture compared to the existing 8-stagger structure memory hole array and a 10% increase in lateral cell array density compared to the 5th generation. The combination of advanced lateral miniaturization technology and 162-level vertical stacking memory has reduced the die size by 40% compared to 112-level vertical stacking memory.

The two companies applied the Circuit Under Array CMOS layout and the four-plane method together to the 6th generation 3D flash memory, achieving a 2.4 times improvement in program performance and a 10% improvement in read latency compared to the previous generation. The input/output (I/O) performance was also improved by 66%, enabling support for next-generation interfaces.

The sixth generation 3D flash memory technology reduces the cost per bit compared to the previous generation and also increases bit production per wafer by 70%. The two companies announced detailed information about this technology through a joint presentation at the 'International Solid-State Circuits Conference (ISSCC) 2021' on the 19th.

Currently, the stacking competition is heating up in the memory semiconductor market. Micron announced the mass production of 176-layer 3D NAND last November, and SK Hynix provided 176-layer 4D NAND samples to customers in December. Samsung Electronics announced that it will apply double stack technology to 7th generation V-NAND with 128 layers or more within this year.