[Editor's Note] When we talk about semiconductors, we tend to think of semiconductors that are familiar to the general public, such as the CPU and memory of computers. On the other hand, MCUs (Micro Controller Units), which are core semiconductors used to operate electronic products, are semiconductors that are still unfamiliar to the general public, even though they are commonly used in all electronic products that we easily come across. These MCUs have recently been in the news due to the semiconductor shortage, and they are beginning to attract the attention of the general public. Accordingly, our magazine has prepared a place to learn about MCUs through a series of articles by Yuji Kawano, Manager of ST Microelectronics, a company specializing in MCU semiconductors.

■ What are CISC and RISC?

You may have seen acronyms like CISC and RISC in MCU catalogs and manuals. What do these acronyms mean and how do they differ from each other? In this paper, we will briefly explain CISC and RISC and examine their respective advantages and disadvantages.

CISC stands for 'Complex Instruction Set Computer', and RISC stands for 'Reduced Instruction Set Computer'. In the complex instruction method, a series of complex processes are performed by executing a single instruction. The CISC architecture uses complex instructions to improve the performance of the MCU. In the reduced instruction method, a simple process is performed very quickly by executing a single instruction. The RISC architecture quickly executes a large number of reduced instructions, thereby improving the overall performance of the MCU.

In this paper, we will explain the characteristics of each method.

■ CISC

The concept of CISC provided the basis for the development of MCU architecture. Around 1970, the combination of computer and semiconductor IC technology led to the realization of MCUs in the form of compact computer IC units. At that time, as electronic calculators became popular, manufacturers all jumped into the competition to develop more useful calculators with better calculation performance.

Even today, companies use different command formats and execution runtimes. The basic rule is to execute as many processes as possible with a single command.

When MCUs were invented, engineers began to focus on developing architectures that would perform each instruction most efficiently. Then, around 1980, a revolutionary MCU architecture called RISC was announced.

■ RISC

Executing complex instructions usually takes a long time, and this requires designing complex logic circuits for MCUs. Conversely, if you can combine a number of simple instructions and execute them quickly, you can perform calculations more efficiently than with CISC. RISC was developed from this idea.

RISC architecture was developed as a result of research at Stanford University and the University of California, Berkeley. The first to announce the development of this new MCU architecture was Patterson and Ditzel. Until now, most MCU experts thought that the only way to increase the overall efficiency of MCUs was to pack as many complex processes into a single instruction as possible, so this new idea was bound to be a great surprise.

RISC architecture uses fixed-length instructions and adopts the concept of a pipeline. Processors are divided into several stages within the pipeline and then executed in small steps through parallel processing. Therefore, RISC appears to execute one instruction per clock cycle (see Figure 1). The architecture also uses other novel methods to execute instructions quickly.





■ Characteristics of CISC

(1) There are no rules regarding the format or length of the command.

Each instruction is designed to have the most appropriate format and size to meet the specifications. Therefore, its execution time depends on the instruction itself. The length of the instruction need not be fixed, because each instruction is designed to maximize processing performance. (If the length of the instruction were fixed, it would actually inhibit the processing efficiency of the pipeline.)

(2) Micro-ROM style command decoding

The micro-ROM method can reduce the size of the logic and perform relatively complex processes, but requires a longer processing time than the random logic method.

(3) Execution of one instruction in one or more clock cycles

Executes a single instruction using one or more clock cycles. The goal is to produce complex process results in a single pass more efficiently overall, even if multiple clock cycles are required.

■ RISC characteristics

(1) Fixed length command

RISC uses fixed-length instructions as part of pipeline processing to achieve fast processing, executing one instruction per clock cycle.

(2) Random logic method instruction decoding

Random logic is adopted to perform fast processing, but one instruction does not correspond to one complex process. In such cases, the micro-ROM method is not efficient.

(3) Single clock processing

Pipeline processing uses a single clock system.

(4) Pipeline processing

As mentioned earlier, in pipeline processing, one instruction is executed per clock cycle.

■ Advantages and disadvantages of CISC and RISC

(1) Size of logic circuit

In the case of RISC, small logic is sufficient because each instruction corresponds to a simple process. However, in the case of CISC, large logic is required because the processes executed for each instruction are complex. For this reason, the micro-ROM method is adopted.

(2) Development cycle

This may not directly affect the end user, but RISC logic circuits require relatively less effort and cost to develop because of their small logic size. However, today's advanced automated design tools can help bridge the gap between large and small logic.

(3) High performance potential

It is difficult to say exactly which one is better in performance. Some CISC MCUs today share some of the advantages of RISC, and some RISC MCUs share some of the advantages of CISC. Therefore, when choosing a type of MCU, you should refer to the benchmark data published for evaluating MCUs, such as MIPS, DMIPS, and COREMARK.

(4) Code density

In CISC architecture, multiple processes are performed by executing one instruction. However, in RISC architecture, multiple instructions are used to perform one process, so RISC is disadvantageous in executing the same processes. The ARM Cortex-M series, a typical RISC product, is designed to adopt both 16-bit and 32-bit instructions to improve code efficiency.

(5) Pipeline hazard

Events such as branch instructions can sometimes create unnecessary cycles that can interrupt the pipeline. This is called a pipeline hazard. In theory, pipeline hazards cannot be completely eliminated, but measures can be taken to minimize the damage. For example, to address branch instruction issues, the Cortex-M series features branch destination prediction.





An overview of this chapter is provided in Table 1.

As the above explanation shows, both CISC and RISC have their own advantages and disadvantages. Therefore, the most practical tip we can give is to choose the MCU that best suits your needs.