Cadence Design Systems (Cadence) announced today that it will continue to strengthen its collaboration with ARM to enable successful tapeout of mobile device silicon by leveraging digital verification tools and ARM’s recently launched Total Compute Solution (TCS23) to provide customers with a “tapeout” path from chip design to manufacturing readiness.

ARM's recently introduced mobile computing platform, the TCS23, includes Arm Cortex-X4, Arm Cortex-A720, and Cortex-A520 CPUs, as well as Immortalis-G720, Mali-G720, and Mali-G620 GPUs.

Through this latest collaboration, Cadence has delivered a comprehensive RTL-to-GDS digital flow Rapid Adoption Kit (RAK) for 3nm and 5nm nodes leveraging ARM’s TCS23 to help customers achieve their power and performance goals.

Cadence tools optimized for ARM's TCS23 include: △Cerebrus Intelligent Chip Explorer △Genus Synthesis Solution △Modus DFT Software Solution △Innovus Implementation System △Quantus Extraction Solution △Tempus Timing Signoff Solution △ECO Option △Voltus IC Power Integrity Solution △Conformal Equivalence Checking △Conformal Low Power, etc.

In particular, Cadence's Cererus provides ARM's AI-based design optimization capabilities, helping ARM maximize the so-called PPA advantages of power, performance, and area by achieving 50% improvement in timing (TNS), 27% reduction in cell area, and 27% improvement in leakage power in the Cortex-X4 CPU.

Additionally, the Rapid Adoption Kit (RAK), which increases productivity through IP verification, provides four key benefits to TCS23 users. First, Cadence Cerebrus automates digital chip design, improving productivity compared to manual methods.

Cadence iSpatial technology provides improved predictability and PPA, along with an integrated implementation flow that ultimately reduces design deadlines.

Additionally, RAK integrates an innovative smart system flow that not only reduces processing times for large-scale, high-performance CPUs, but also provides path-based analysis to accurately finalize designs. And RAK dramatically reduces dynamic power consumption by leveraging the activity-aware power optimization engine of Cadence Innovus Implementation System.

Cadence provides ARM TCS23 users with a verification flow that improves overall verification throughput and enables state-of-the-art software debug capabilities. Additionally, Cadence's comprehensive verification solution VIP supports the TCS23, enabling customers to shorten time to market when assembling TCS23-based SoCs.

This includes ARM Fast models that support early software development and verification with Cadence Helium Studio, as well as Cadence’s Palladium and Protium platforms, collectively known as the “Dynamic Duo,” for virtual and hybrid platform reference designs.

“With the introduction of the ARM TCS23, we are unlocking the creative potential of customers around the world who demand high-performance, efficient compute to power the next generation of mobile experiences,” said Chris Bergey, senior vice president and general manager, client business unit, ARM. “Working with Cadence to successfully leverage the Cadence Digital Verification Flow has enabled us to deliver the latest CPUs and GPUs to our customers more quickly, accelerating their time to market.”

The Cadence Digital Verification Flow supports the Cadence Intelligent System Design strategy, which helps customers achieve SoC design excellence.

“The new ARM TCS23 provides designers with the best possible experience by creating the world’s most advanced mobile designs,” said Chin-Chi Teng, senior vice president and general manager, Cadence Digital & Sign-off Group. “We’ve been collaborating with ARM on the development of the TCS23 to deliver an innovative digital verification flow that will help customers improve overall productivity and accelerate time to tapeout.”