컴퓨터 관련 주요 부품 수입 유통 전문 업체 서린씨앤아이(대표 전덕규)가 ADATA(에이데이타)의 PC메모리, 랜서(LANCER) RGB 시리즈를 정식 출시했다.
16GB x 2 configuration 32GB dual kit 32GB x 2 configuration 64GB dual kit
Serin C&I (CEO Jeon Deok-gyu), a major computer-related parts import and distribution company, has officially launched ADATA's PC memory, the LANCER RGB series.
Lancer RGB is a high-performance PC memory belonging to XPG (Xtreme Performance Gear), ADATA's own gaming hardware brand.
The platform supports DDR5 with an operating clock of 6400MHz (51200MB/s) and CL32 RAM timing.
The capacity is divided into a 32GB dual kit with 2 x 16GB and a 64GB dual kit with 2 x 32GB, and a total of 4 types are prepared, divided again into black and white according to the color of the heatsink.
ADATA completed the sensational appearance by adding a diagonal line on the side of the Lancer RGB's heatsink and a light-emitting area connecting the RGB LED bar at the top. In particular, the heatsink, divided into black and white, helps complete the system's coloring combination while also improving heat dissipation performance.
The lighting area of the Lancer RGB supports various settings not only through RGB control programs of major motherboard manufacturers such as ASUS, ASRock, GIGABYTE, and MSI, but also through the company's own software, XPG Prime. It supports color, pattern, and brightness of the lighting area, as well as system monitoring or detailed adjustment of functions through various hardware products of the company.
ADATA has applied SK Hynix’s high-quality ICs and Un-Lock PMICs to its various high-performance memory lineups, including Lancer RGB. This enables compatibility regardless of CPU platform and stable performance even in overclocking environments. It also provides optimized system resources for various system environments, such as overclockers, hardcore gamers who require extreme computing environments, and artists and editors who need to utilize high-capacity resources.
Lastly, Lancer RGB supports users with unique features of the DDR5 platform, such as high-speed data transmission using a 32-bank architecture and data integrity support of ODECC (On-Die Error Correction Code).