[Editor's Note] Generally, when we think of semiconductors, we tend to think of semiconductors that are familiar to the general public, such as the CPU and memory of computers. On the other hand, MCUs (Micro Controller Units), which are core semiconductors used to operate electronic products, are semiconductors that are still unfamiliar to the general public, even though they are commonly used in all electronic products that we easily come across. These MCUs have recently been in the media due to the semiconductor shortage, and have begun to attract the attention of the general public. Accordingly, our magazine has prepared a place to learn about MCUs through a series of articles by Yuji Kawano, Manager of ST Microelectronics, a company specializing in MCU semiconductors.

■ Question

What types of latch-ups tend to occur in the MCU?

■ Answer

The MCU consists of a large number of PN junctions, some of which form quadruple-layer PN junctions (PNPN junctions), which in turn form parasitic thyristors.

A thyristor is a switching element for power control. It consists of three terminals: an anode, a cathode, and a gate.

In normal conditions, no current flows from the anode to the cathode, but when a signal is applied to the gate, current begins to flow from the anode to the cathode.

Once current starts flowing, it will not stop until the power is cut off.

In order to pass large currents, the on-resistance must be very small. The same phenomenon can occur in parasitic thyristors inside MCUs, and this phenomenon is called latch-up.

A latch-up event inside the MCU generates a large current that can not only cause a failure, but in the worst case, melt the wiring or destroy the internal MCU components.

Latch-up does not occur during normal use, but it can be induced by errors during power-up or sudden increases in high-voltage noise on the terminal. Figure 1 shows a photo of a metal line on the surface of an MCU melted due to latch-up.





■ Description
○ Thyristor structure

Figure 2(a) shows the structure of a PNPN thyristor. When a positive voltage is applied to the anode and a negative voltage is applied to the cathode, no current flows from the anode to the cathode. This is because a backward voltage is applied to J2 and a forward voltage is applied to J1 and J3 respectively.

However, if a voltage is applied to the gate to allow current to pass, the resulting gate current will increase the reverse current through J2, significantly increasing the amount of current that flows from the anode to the cathode. This is because a forward voltage is already applied to each of J1 and J3. Once the current starts flowing, it will continue until the power supply to the anode is cut off.

This describes the switching operation of a thyristor, which is used as a switching element in power equipment.

As shown in Figure 2(b), the PNPN junction is equivalent to integrating a PNP transistor and an NPN transistor. This two-transistor structure is shown in the circuit diagram of Figure 2(c).

The Tr1 emitter (E) acts as the anode of the thyristor. The base is the Tr1 collector (C) (Tr2 base (B)). The Tr2 emitter (E) acts as the cathode of the thyristor.





These two transistors in the CMOS structure of the MCU are shown in Figure 3.





○ Latch-up event mechanism

Both N-SUB (see Figure 3) and P-SUB result in parasitic PNPN junction structures, and the latch-up event mechanism is the same for both.

Tr1 consists of a circuit consisting of a PMOS source Pch connected to the power supply, N-SUB, and P-WELL. Tr2 consists of a circuit consisting of an NMOS source Nch connected to N-SUB, P-WELL, and GND.

In the CMOS structure, Tr1 and Tr2 are configured as indicated by the yellow line in Figure 3. The power is connected to the anode, the cathode is connected to GND, and the gate corresponds to the P-WELL of the NMOS structure.

The CMOS input lines are connected to the NMOS gates. The gate, P-WELL, and the gate oxide film located between them form a capacitor, which easily passes high frequencies. If noise with a large dV/dt (large high-frequency component) characteristic is introduced along the input line, such noise can pass through the gate oxide film and reach the P-WELL. This causes the PNPN junction to turn on, resulting in a large current being supplied from the power supply to the GND.

If the voltage on the power line changes rapidly, especially in the negative direction, the gate voltage will rise above the power supply voltage, resulting in the same conditions as when noise is introduced into the gate. This condition causes voltage to be applied to the terminals before the MCU power supply is protected.

Since the MCU has a very large number of PNPN junctions, it is impossible to predict which PNPN junction will cause a latch-up.

○ Cause of latch-up

In summary, the causes of latch-ups in MCUs are as follows:

(1) External noise coming from the terminal
External noise with large dV/dt characteristics as well as sharp rising and falling edges can reach deep inside the MCU and turn on certain PNPN junctions. Although noise can generally be thought of as consisting of electromagnetic waves, high voltages of electrostatic charge also generate noise.

(2) Power supply noise
When noise affects the power supply, the voltage decreases, creating the same conditions as the noise entering the gate of the PNPN junction, which can cause latch-up. Such cases include cases where voltage is applied to the terminals before the MCU power supply is protected. The result is the same as when external noise affects the terminals.

(3) Gate noise caused by internal voltage fluctuations within the MCU
When a relatively large current passes through the MCU, a potential difference is created inside it, which can cause the same phenomenon as operating the PNPN junction gate. This is also a cause of latch-up. This phenomenon occurs when a large current flows into the power supply or through the GND. Similarly, a large current passing through the terminals can change the voltage inside the MCU, causing latch-up.

○ Prevention method

You can prevent latch-up from occurring by eliminating the causes mentioned above through the following methods.

(1) Blocking noise coming through the terminal
If you are using the MCU in a noisy environment, you need to block the noise from the terminals. If you cannot prevent the noise, you need to reduce the dV/dt of the noise by using shielding, limiting resistors, capacitors, ferrite cores, etc.

(2) Compliance with prescribed power-on procedures;
Some MCUs can use multiple power supplies, and the user manuals describe the procedures and precautions for powering them to the ON state. Be sure to follow the power-on procedures specified in the manual. Also, be sure to follow the power-up intervals specified in the manual or datasheet.

(3) Overcurrent protection for power lines and terminals
The maximum current value is specified in the user manual or data sheet. Because applying high voltage can cause overcurrents, it is imperative that you adhere to the values specified in the user manual (especially the maximum ratings).

(4) If there is a possibility that a large current may pass through the MCU due to latch-up, an effective way to protect the MCU is to install a protection circuit that cuts off the power when an overcurrent is detected. Since the large current caused by the latch-up is stopped when the power is cut off, the protection circuit protects the MCU from damage. If there is no failure in the MCU, it will return to normal operation when the power is turned on again.