Heterogeneous Integration (HI) is an advanced solution that increases performance and density while reducing costs. Due to the limitations of fine processes, the semiconductor industry is actively moving at the package level. Applied's newly released heterogeneous integration manufacturing solution is contributing to the achievement of Moore's Law at the package level by improving the PPACt (power, performance, size, cost, and time to market) of chips.

Applied Materials, a global leader in materials engineering solutions, today announced the introduction of materials, technologies and systems that help integrate chiplets into the latest 2.5D and 3D packages using hybrid bonding and through-silicon via (TSV) processes.

Heterogeneous bonding allows semiconductor companies to combine chiplets of different functions, technology nodes, and sizes into a modern package that functions as a single product. In areas such as high-performance computing and artificial intelligence (AI), the need for transistors is growing exponentially, while shrinking transistors through conventional 2D scaling is slow and more expensive.

Heterojunctions are receiving significant attention from the industry as a key part of a new playbook that will help semiconductor manufacturers improve the PPACt (power, performance, size, cost, and time to market) of their chips in new ways.

Applied Materials is the largest heterojunction manufacturing technology company with optimized chip manufacturing systems encompassing etching, physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, chemical mechanical polishing (CMP), heat treatment, and surface treatment.

“Heterojunction chip technology is growing rapidly because it helps overcome the limitations of conventional 2D scaling, which cannot simultaneously improve performance, power and cost,” said Sundar Ramamurthy, vice president and general manager of HI, ICAPS and Epitaxy for Applied Materials’ Semiconductor Products Group. “Applied’s latest HI solutions advance the state-of-the-art by packaging more transistors and interconnects in 2.5D and 3D configurations, enabling higher system performance, lower power consumption, smaller size and faster time to market.”

■ Stronger Hybrid Bonding

Chip-to-wafer and wafer-to-wafer hybrid bonding uses direct copper-to-copper bonds to connect chips, allowing the bonded devices to perform as a single product. Hybrid bonding is the most advanced heterojunction technology available today, improving throughput and power by packing more wiring into a smaller space and reducing the distance signals have to travel.

Applied's Insepra SiCN deposition system expands Applied's portfolio of leading hybrid bonding products. The system uses a novel silicon carbon nitride (SiCN) material that delivers industry-leading dielectric bond strength and superior copper diffusion barrier properties. The strong dielectric bond provides the structural stability needed to integrate significantly more copper-to-copper interconnects into a given area, reducing power consumption and improving device performance.

The Catalyst CMP solution, also launched with the new product, enables customers to control the amount of “dishing,” which is the intentional concave-convexity of the copper material between the two surfaces to be joined in a subsequent high-temperature heat treatment step. CMP dishing can cause unwanted metal loss to the top surface of the copper pad, creating an air gap that reduces the integrity and strength of the copper-to-copper bond. Applied’s Catalyst solution is a dynamic temperature control technology that reduces dishing and increases throughput.

■ TSV with higher aspect ratio

TSVs, which have been used in semiconductor mass production for more than a decade, are vertical wires that precisely connect stacked chips. They are made by etching trenches in silicon and then filling them with insulating films and metal wires. As more logic, memory, and specialized chips are integrated into the latest 2.5D and 3D packages, the number of TSV interconnects is increasing from hundreds to thousands per package. To integrate more interconnects and accommodate taller chip stacks, vias must be made narrower and taller, which reduces deposition uniformity, lowers performance, and increases resistance and power consumption.

Applied Semiconductor unveiled new technologies for dielectric and metal deposition that enable higher aspect ratio TSVs and help semiconductor manufacturers achieve their integration, performance, and power goals.

The Producer InVia 2 CVD system is a novel CVD process that provides uniform, electrically robust dielectric liners at the extreme aspect ratios required by logic and memory customers in a variety of TSV applications. The InVia 2 system utilizes a unique in-situ deposition process that provides exceptional suitability for high aspect ratio TSVs. By delivering higher productivity than atomic layer deposition (ALD) technologies, it can further accelerate adoption by reducing the cost per wafer for TSVs.

The Endura Ventura 2 PVD system extends a widely adopted existing product to TSV applications with aspect ratios up to 20:1. The Ventura 2 system improves the control of metal TSV wire deposition for complete fill that delivers high electrical performance and reliability.

The new TSV PVD process is optimized for use with Producer’s InVia 2 CVD process, providing customers with a ready solution for their most demanding TSV designs. The Ventura 2 system is in use by all leading-edge foundries and logic chip manufacturers, as well as all major DRAM manufacturers.

Applied's latest Producer Avila PECVD system is designed for TSV 'reveal' applications. In the TSV process flow, the wafer is temporarily bonded to a glass or silicon carrier and then thinned using CMP and etching to enable TSVs.

Following the TSV Reveal step, a thin dielectric layer that electrically isolates the TSV is deposited using plasma CVD technology. The PECVD process generates heat in excess of 200 degrees Celsius, which can damage the delicate temporary bonds and result in wafer yield loss. The Applied Producer Avila PECVD system produces high-quality dielectric films at high speeds at ultra-low temperatures, providing the low heat budget and high productivity required for TSV quality and cost.

More information about the newly launched Applied solutions and systems can be found on the Applied website.