Intel CEO Pat Gelsinger said the next step after Moore's Law will be multi-chiplet packages, and also unveiled a test chip package based on the Universal Chiplet Interconnect Express (UCIe).

Intel held its third annual developer event, Intel Innovation, in San Jose, California, USA on the 19th.

At this year’s event, Intel unveiled a range of technologies designed to make AI accessible and usable across all workloads, from client, edge, network and cloud.

First, CEO Gelsinger said that Intel's goal of developing a five-node process over four years is progressing without a hitch.

Currently, mass production is already underway with the Intel 7 process, the Intel 4 process is ready for manufacturing, and Intel 3 is scheduled to be ready for manufacturing by the end of this year.

Gelsinger CEO unveiled the first test chip and Intel 20A wafer for Intel's Arrow Lake processor, which will hit the PC market in 2024.

Intel 20A is the first process to feature PowerVia, a rear-side power delivery technology, and a new gate-all-around (GAA) transistor design called RibbonFET.

Intel 18A, the second process to utilize PowerVia and RibbonFET, is also scheduled for 2024. Production preparations are expected to be completed in the second half of the year.


Intel is continuing Moore's Law in a different way, with new materials like glass substrates and new packaging technologies, among other innovations it announced this week.

Glass substrates are expected to continue to increase the number of transistors that can be packed into a package beyond 2030, helping to meet the demands of data-intensive, high-performance workloads such as artificial intelligence.

Intel also unveiled a test chip package based on its Universal Chiplet Interconnect Express (UCIe) today.
Gelsinger said the next phase of Moore’s Law will come with multi-chiplet packages, as open standards make IP integration easier. The UCIe standard, released last year, enables chiplets from different suppliers to work together, enabling new designs to scale diverse AI workloads. Currently, more than 120 companies are participating in the UCIe standard.

The test chip announced by Intel today combines an Intel UCIe IP chiplet based on the Intel3 process and a Synopsys UCIe IP chiplet based on the TSMC N3E process. The chiplets are connected using the embedded multi-die interconnect bridge (EMIB) advanced packaging technology. Through the technology demonstration, Intel emphasized the commitment of TSMC, Synopsys, and Intel Foundry Services (IFS) to support an open, standards-based chiplet ecosystem based on UCIe.

On that day, Intel announced that it would be releasing the 5th generation Intel Xeon processor on December 14th, providing data centers around the world with a combination of improved performance and faster memory.

Sierra Forest, featuring E-Core efficiency, scheduled to be announced in the first half of 2024, will deliver 2.5x higher rack density and 2.4x higher performance-per-watt than 4th-generation Xeon processors, and will also feature 288 cores2.

High-performance P-core-based Granite Rapids, scheduled to be released around the same time as Sierra Forest, is expected to deliver AI workload performance that is 2-3x faster than 4th generation Xeon processors.

The next-generation E-core-based Xeon processor (codenamed Clearwater Forest), scheduled for launch in 2025, will be produced based on Intel's 18A process.

An AI PC equipped with an Intel Core Ultra processor was also introduced.

Intel is delivering a new PC experience based on the Intel Core Ultra processor (codenamed Meteor Lake), which features the first integrated neural processing unit (NPU).

NPUs support power-efficient AI acceleration and local inference capabilities on PCs. Gelsinger CEO said that Intel Core Ultra processors will be released on December 14th.

The Intel Core Ultra processor represents a major milestone in Intel’s processor roadmap for PCs. It is the first chiplet-based product for PCs to use Intel’s Foveros packaging technology.

Power efficiency has been significantly improved based on NPU and Intel 4 process technology, and the built-in Intel® Arc™ graphics provide graphics performance equivalent to external graphics.

Gelsinger CEO showcased a variety of AI PC use cases on stage, while Acer COO Jerry Kao revealed some upcoming Core Ultra-based notebooks.

“Acer has been co-developing a series of AI applications with Intel to leverage the Intel Core Ultra platform,” said Kao. “We are developing them using the OpenVINO toolkit and the co-developed AI libraries to bring the hardware to life.”