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Intel Unveils “Structured eASIC” Combining the Strengths of FPGAs and ASICs

기사입력2020.11.18 16:50

Customer-specific logic and Intel eASIC N5X
Design utilizing FPGA built-in hard processor
Migration to structured ASICs possible



On the 18th, Intel held 'FPGA Technology Day' and announced 'Intel eASIC N5X', a new customized solution that accelerates application performance across 5G, AI, edge, and cloud workloads.
▲ Intel Unveils eASIC N5X [Image = Intel]

The Intel eASIC N5X is the first structured eASIC family that embeds an Intel FPGA-compatible hard processor system. With the Intel eASIC N5X, customers can migrate designs that utilize customer-specific logic and hard processors embedded in FPGAs into a “structured ASIC.”

“The Intel eASIC N5X enables customers to enjoy the flexibility and time-to-market benefits of Intel FPGAs with the enhanced performance and lower power of structured ASICs,” said Dave Moore, Intel vice president and general manager of the Programmable Solutions Group. “No other company in the market today can offer the comprehensive custom logic offering that Intel does.”

FPGAs offer customers short time-to-market and maximum flexibility when designing their own products. Programmable FPGAs allow rapid hardware development for specific workloads and adaptability to changing standards. ASICs and structured ASICs provide hardware performance optimization at low power and cost.

Intel eASIC N5X boasts up to 50% lower core power consumption and up to 50% lower price than FPGAs. It also offers shorter time to market and lower non-recurring engineering costs compared to ASICs.

Additionally, it integrates the security device manager adopted from the Intel Agilex FPGA family, including secure boot, authentication, and anti-tamper features, enabling customers to address key security requirements for many applications.
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