EUV, with a shorter wavelength than ArF, improves semiconductor processes
EUV process requires power source and causes severe metal contamination
Parallel use with DPT/QPT processes below 5nm


Moore's Law is the law that semiconductor chip performance doubles every 18 months. Based on this law, which was claimed by Intel co-founder Gordon Moore in 1965, semiconductor companies have established their manufacturing strategies.

However, since the 2010s, the performance of semiconductor chips has slowed down due to the increasing difficulty of process miniaturization, raising many questions about Moore's Law. However, Moore's Law is expected to be extended as the Extreme Ultra Violet (EUV) process is fully introduced to the semiconductor process.

According to the Korea Semiconductor Industry Association (KSIA), the wavelength of EUV is 13.5 nm, which is much shorter than the 193 nm of argon fluoride (ArF), which has been widely used so far, and can increase the precision of semiconductor exposure processes.

The EUV process, which is attracting attention as a method to realize next-generation semiconductor microfabrication, is currently being applied mainly in logic and foundry processes. In both fields, it is more cost-effective to use the EUV process than the DPT (Double Patterning Technology)/QPT (Quadruple Patterning Technology) process at 7nm and below.

However, the industry expects that rather than achieving cost competitiveness by using only EUV technology, the direction will be to have EUV technology take charge of some of the fine processes. EUV is very difficult to implement, to the point that it requires a separate power plant for power sources, and metal contamination is also severe.

Currently, the industry mostly uses existing ArF immersion equipment to implement fine patterns. ArF immersion can theoretically be used up to the 40nm process. For the 30nm process and below, the DPT process is additionally used in ArF immersion equipment.

EUV can be used to implement 7nm and 5nm processes without repeating the exposure process. The problem is mass production. Therefore, it is expected that the technology will be developed in the direction of using EUV locally in areas where fine patterns are required and using the existing immersion process in other areas.

In addition, if a process below 5nm needs to be implemented with EUV, the problem of having to introduce the DPT process to EUV arises. Therefore, it seems that the DPT and QPT processes will have to be used together with EUV for the 5nm process and below.

It is expected that future exposure processes will be developed by combining various technologies rather than applying a single technology. Process miniaturization is expected to continue through EUV technology and the development of alternative technologies, including DPT and QPT, which are existing exposure repetitive processes.

◇ Semiconductor structures and materials will also change with the introduction of EUV

In the logic and foundry fields, EUV is being introduced after 7nm, and 3D structure technology development is also being carried out in parallel.

Up to the 5nm or 4nm process, EUV will be used exclusively, but below 5nm, DPT or QPT technology will be applied to EUV technology, and the structure is also expected to change to the GAA (Gate-All-Around) method that surpasses FinFET.

In the DRAM field, EUV technology will be introduced in earnest after 1zm, and diversification of material technologies such as hafnium oxide (HfO2) in the cap process is expected.