Ethernet Bandwidth Increasing Trend, FPGA Usage Spreads
FPGA, Fast Processing of Ethernet Payload Data
Quarters Ethernet Toolkit, Design and Debugging Support


As the demand for large-capacity data transmission increases, Ethernet bandwidth expansion has also been steadily increasing. However, the spread of 5G and IoT, the increase in AR, VR, and 4K content, the activation of the cloud, and the spread of telecommuting and remote work are adding to the traffic on wired and wireless infrastructure.

One of the ways to implement high-speed Ethernet is to replace the Ethernet controller with an FPGA. FPGAs have the advantage of being able to optimize performance to suit the user's purpose. However, if you do not have FPGA-based knowledge and experience, it is not easy to utilize.

FPGA manufacturers are also aware of the difficulties faced by the field, and are providing various design materials and verification tools for customers who wish to adopt FPGAs instead of Ethernet controllers.

We asked Hyung-Sook Kim, a manager in charge of Intel FPGA technical support at Uniquest, about how to easily implement high-speed Ethernet and how to verify the implemented network.



Q. What are the benefits of adopting FPGAs in implementing high-speed Ethernet?

A. Implementing high-speed Ethernet using FPGAs instead of commercial Ethernet controllers allows the FPGA to process Ethernet payload data that the host needs to handle with low latency, reducing the workload of the server CPU.



Q. Among Intel FPGA products, the 'Arria 10' series and 'Stratix 10' series are mainly used for Ethernet implementation. What is the difference between the two?

A. Intel provides both PHY and MAC hard IPs for the Stratix 10 series, the higher-end model of the Arria 10 series. On the other hand, the Arria 10 series provides only hard IPs for PHY, and only soft IPs for MAC.



IP(Intellectual Property) is a reusable functional block with independent functions used in circuit design such as SoC(System on Chip) and FPGA(Field Programmable Gate Array). It is usually divided into soft IP in the form of RTL(Register Transfer Level) code that can be synthesized into logic, and hard IP in the form of design data that has been placed and routed according to a set process. Hard IP is easier to implement functions than soft IP.



Q. What are the advantages of implementing the PHY and MAC of high-speed Ethernet with hard IP?

A. Ethernet speed and operating clock are proportional. If PHY and MAC are implemented as hard IP, they are not affected by other logic, so the timing of the Ethernet hard IP operating clock does not change. The delay is also shorter than when implemented as soft IP. In addition, the internal resources of the FPGA occupied by the soft IP can be used to implement other logic.



Q. What are the features of the transceiver tiles of the Stratix 10 series provided by Intel, such as △H-tile, △P-tile, and △E-tile?

A. H-tile is similar in structure to the transceiver of the Arria 10 series. It supports 28.3G NRZ and implements PCIe gen3 x16 and 50/100G Ethernet MAC as hard IP. P-tile is a PCIe-only transceiver tile with PCIe gen4 x16 implemented as hard IP.

E-tile supports 28.9G NRZ and 57.8G PAM-4, and implements 10/25/100G Ethernet MAC and RS-FEC as hard IP, reducing soft MAC IP costs.



Q. What are the typical things to check to verify normal operation after building a High-Speed Ethernet PHY and MAC?

A. Since the PHY is configured with an Intel FPGA transceiver, the transceiver operation is checked with signals such as △cdr_lock, △rx_block_lock, △tx_pll_locked, △ehip_ready, and △tx_lanes_stable. Then, the Ethernet IP output clock must be checked.



Q. What tools does Intel provide for FPGA-based high-speed Ethernet verification?

A. The Ethernet Toolkit is an Ethernet debugging tool provided free of charge through 'Intel® Quartus® Prime' and is not provided by competitors. The Ethernet Toolkit can be used immediately with only the Intel FPGA Download Cable.



The Ethernet Toolkit allows users to view the status of FPGA-based Ethernet connections in real time, and access the configuration and status registers of the Ethernet IP. More information can be found in the e4ds EE Webinar starting at 10:30 AM on Tuesday, June 3.