TSMC가 고급 패키징 및 테스트를 위한 후공정 팹 신공장을 가동하며, 첨단 반도체 생산 수율과 효율성 개선에 나섰다.
3DFabric™ Advanced Packaging and Silicon Stacking for Flexible Capacity Allocation
Annual production of over 1 million 12-inch wafers using 3DFabric process technology
TSMC has started operation of a new back-end fab for advanced packaging and testing, improving yields and efficiency in advanced semiconductor production.
TSMC announced the opening of Advanced Backend Fab 6, its first all-in-one automated advanced packaging and test fab, on the 8th.
The fab is ready for mass production of TSMC-SoIC™ (System on Integrated Chips) process technology.
Advanced back-end Fab 6 will allow TSMC to flexibly allocate capacity for SoIC, InFO, CoWoS and advanced test, as well as TSMC’s 3DFabric™ advanced packaging and silicon stacking technology, improving production yields and efficiency.
Construction began on the advanced back-end Fab 6 in 2020 to support next-generation HPC, AI, mobile applications and other products, helping customers achieve product success and market opportunities.
Located in Zhunan Science Park, the fab has a base area of 14.3 hectares, with a larger cleanroom area than TSMC's other advanced back-end fabs combined, making it TSMC's largest advanced back-end fab to date.
TSMC estimates that the fab will have the capacity to produce more than 1 million 12-inch wafer-equivalent 3DFabric process technology units per year and more than 10 million hours of test services per year.
TSMC uses intelligent manufacturing to improve fab production efficiencyThe castle has been optimized.
The total length of the 5-in-1 intelligent automatic material handling system built into the factory exceeds 32 km.
Shorten production cycles by connecting production information from wafer to die with agile dispatch systems. These systems are combined with artificial intelligence to simultaneously perform precise process control, detect anomalies in real time, and build a robust die-level big data quality defense network.
Its data processing capacity is 500 times that of a full-process fab, and die traceability creates a complete production history for each die.
“Chiplet stacking is a key technology to improve chip performance and cost efficiency,” said Dr. Jun He, Vice President of Operations/Advanced Packaging Technology and Services, Quality and Reliability Division at TSMC. “In response to the strong market demand for 3D ICs, TSMC has completed early deployment of advanced packaging and silicon stacking technology production capabilities and provides technology leadership through the 3DFabricTM platform,” the company said.
Meanwhile, e4ds will hold the '
2023 e4ds Semiconductor Packaging Day' at the Korea Conference Center Grand Hall on June 28.n Sans", "Helvetica Neue", Helvetica, Arial, sans-serif; font-size: 15.4px; letter-spacing: 1px; word-spacing: 2px; background-color: rgb(249, 249, 249);">' event. At this seminar, top domestic and international packaging experts, including Intel, Nepes, Applied Materials, Hanyang University, and Hyundai Motor Securities, will present on next-generation packaging solutions. Participation in the event is '
2023 e4ds Semiconductor Packaging Day ' (;Malgun Gothic", "Nanum Gothic", "Open Sans", "Helvetica Neue", Helvetica, Arial, sans-serif; font-size: 15.4px; letter-spacing: 1px; word-spacing: 2px;" target="_blank">https://www.e4ds.com/seminar_introduce.asp?idx=137
) can be done on the homepage.