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Intel Unveils Next-Generation Packaging 'Glass Substrate' Technology

기사입력2023.09.19 09:16


▲Hamid Azimi, Intel Vice President and Director of Substrate Technology Development, holding a glass substrate test chip assembled by Intel (Photo: Intel)
Limitations to Organic Packaging by 2030
Glass substrates can significantly improve scalability, performance, and integration.
One trillion transistors integrated into a single package by 2030

The semiconductor industry is seeking answers to Moore's Law in next-generation, advanced packaging. Intel has found a clue in glass, a material that offers greater scalability.

Intel announced on the 19th one of the industry's first glass substrates for next-generation advanced packaging, which is expected to be available by 2030.

Compared to today's organic substrates, glass offers superior properties, such as very low flatness and better thermal and mechanical stability, enabling significantly higher interconnect density on the substrate. These advantages enable chip designers to create high-density, high-performance chip packages for data-intensive workloads like AI.

Intel plans to bring a complete glass substrate solution to market by 2030. By 2030, the semiconductor industry will likely reach its limit in scaling transistors on silicon packages using organic materials. Organic materials have limitations, such as lower power efficiency and shrinkage and warping. Scalability is crucial for the advancement and evolution of the semiconductor industry, and glass substrates are a viable and essential step toward realizing next-generation semiconductors, Intel explained.


▲Glass substrate test panel (Photo: Intel)

As the semiconductor industry enters a heterogeneous era where multiple "chiplets" are mounted within a single package amidst increasing demands for more powerful performance, improvements in package substrate signal speed, power supply, design rules, and stability have become essential.

Glass substrates possess superior mechanical, physical, and optical properties that enable the interconnection of more transistors within a package. Furthermore, they offer greater scalability than the organic substrates currently used in the industry, enabling the assembly of larger chiplet complexes, also known as system-in-package. Chip designers can accommodate more tiles (or chiplets) within a smaller space within a single package, achieving improved performance and integration with greater flexibility and lower overall cost and power consumption.

The introduction of glass substrates is expected to be first adopted in industries that handle workloads and applications requiring large form factors, such as data centers, artificial intelligence, and graphics, and that demand high speeds.

Glass substrates offer high-temperature durability and a 50% reduction in pattern distortion. Furthermore, their extremely low flatness improves lithographic depth of focus and provides the structural stability necessary for extremely dense interlayer interconnect overlays. These unique properties enable a tenfold increase in interconnect density on glass substrates. Furthermore, the improved mechanical properties of glass enable the implementation of ultra-large form factor packages with very high assembly yields.

The high-temperature endurance of glass substrates allows chip designers to apply more flexible design rules for power supply and signal routing. This allows for seamless integration of optical interconnects and the ability to handle inductors and capacitors within the glass at higher temperatures. This allows for better power supply solutions while delivering signals at the required speeds at lower power levels. These advantages bring chip designers one step closer to the goal of integrating one trillion transistors in a single package by 2030.

▲Glass substrate test panel (Photo: Intel)

For over a decade, Intel has been researching and validating the reliability of glass substrates as a replacement for organic substrates. Intel spearheaded the transition from ceramic to organic packaging in the 1990s and pioneered halogen- and lead-free packaging. Furthermore, Intel developed advanced embedded die packaging technology, enabling the industry's first active 3D integration technology. Intel has been able to activate an entire ecosystem around these innovative technologies, encompassing suppliers of equipment, chemicals, raw materials, and even substrate manufacturers.

“After 10 years of research, Intel has secured an industry-leading glass substrate for advanced packaging,” said Babak Sabi, vice president and general manager of Intel’s Assembly and Test Technology Development Division. “We expect to deliver cutting-edge technology that will benefit our key industry and foundry customers for decades to come.”

Meanwhile, Intel recently demonstrated its commitment to next-generation computing beyond Intel's 18A process node by using industry-leading glass substrates in advanced packaging, following groundbreaking technologies like PowerVia and RibbonFET. Intel is striving to integrate one trillion transistors into a single package by 2030 and will achieve this goal through continued innovation in advanced packaging, including glass substrates.