최근 파네시아가 미국 캘리포니아주 산타클라라에서 열린 제1회 CXL 컨소시엄 개발자 컨퍼런스 2024에 참가해 CXL 상호운용성 검증을 시연했다.

▲Panesia booth site photo / (Photo: Panesia)
CXL Interoperability Verification with Intel and AMD CPUs
Panesia, “Intel, HPE, etc. are very interested”
Samsung and SK also exhibit CXL memory solutions
Recently, Panesia participated in the first CXL Consortium Developer Conference 2024 held in Santa Clara, California, USA, and demonstrated CXL interoperability verification.
At this event, which was attended by global IT companies such as AMD, Intel, and HPE, Panesia said it received attention from participants by demonstrating interoperability verification with Intel and AMD's CXL CPU. Panesia presented an 'interoperability verification demo' that showed that its self-developed CXL IP normally exchanges messages with commercially available CXL CPU devices from Intel/AMD in compliance with the CXL standard.
The “CXL 3.1 All-in-One Framework,” a solution that consists of all system components with CXL 3.1 devices developed in-house, was also exhibited, and according to officials, executives and employees of various global IT companies such as Qualcomm, Hewlett Packard Enterprise (HPE), Intel, AMD, Micron, Huawei, Synopsys, and Teledyne LeCroy have shown interest in Panesia’s products and interoperability demos.
A Panesia official said, “In particular, many people from Intel and Hewlett Packard Enterprise visited,” and “An Intel official said after seeing Panesia’s demo and exhibits, ‘This is the most advanced CXL technology I’ve ever seen,’ and an Hewlett Packard Enterprise official said about Panesia’s CXL switch-based solution, ‘It’s a very interesting and reasonable solution. ’”
CXL DevCon 2024, held for the first time this year, is an official conference hosted by the CXL Consortium, which establishes the CXL standard, and Panesia is also a member of the consortium and is leading CXL technology.
Samsung Electronics and SK Hynix are participating domestically, and at CXL DevCon, Samsung introduced its CMM-D (DRAM-based CXL Memory Module) and CMM-H (hybrid CXL Memory Module) solutions.
SK Hynix is developing the next-generation CXL solution, CMM-DDR5 (DDR5-based CXL Memory Module), and the CXL Disaggregated Memory Solution (CXL Disaggregated Memory Solution).on) Niagara 2.0, and the latest CXL memory technology targeting AI.
Meanwhile, after the CXL DevCon event, Panesia will attend the Open Compute Project (OCP) meeting as a presenter to present Panesia’s next-generation data center switch solution. It has been reported that Panesia will visit the U.S. campuses of several global IT companies that have been discussing collaboration with Panesia on a regular basis to hold business meetings.
CSO Kwon Mi-ryeong expressed her ambition, saying, “During this business trip, I will introduce Panesia’s differentiated technology and vision to various global companies.”