Recently, the global big tech companies are in full swing in their development of large-scale AI. In addition, as large-scale AI evolves into larger and more complex models, the demand for AI accelerators and memory expansion is inevitable. CXL (Compute Express Link) is the next-generation interface technology that solves this problem, and global large corporations are rushing to develop CXL technology and build an ecosystem.

On the 23rd, domestic fabless company Panesia announced that it will be the first Korean startup to demonstrate CXL interoperability on the global stage. It will participate in the 1st CXL Consortium Developer Conference 2024 (CXL DevCon 2024) and announce a next-generation CXL 3.1 switch-based solution.

■ Next-generation semiconductor technology 'CXL'

CXL automatically guarantees a series of operations, such as cache coherence management, required for memory management. It is a technology that can optimize the performance and efficiency of data centers by flexibly expanding memory according to the needs of the device.

It has recently attracted the attention of global big tech companies such as Microsoft (MS) and Meta, as it offers high performance efficiency and is also affordable.

CXL is strengthening its practicality through standardization. After CXL 1.0 was proposed in 2019, the CXL 2.0 standard was established with improved scalability utilizing the CXL switch. Recently, the CXL 3.0 and 3.1 standards were announced, which support the function of sharing memory among multiple users to maximize memory resource utilization.

Currently, global giants such as Intel and AMD are focusing on the development of CXL technology, and efforts such as interoperability verification to check whether system device manufacturers are operating properly in accordance with the CXL standard are required to build a CXL ecosystem.

■ CXL interoperability verification and CXL 3.1 IP all-in-one framework
Panesia is a CXL semiconductor fabless startup that develops and supplies CXL IP and switches. The IP implements CXL interface functions as circuit blocks to enable the introduction of CXL technology into various system devices.

While developing chips such as AI semiconductors and memory semiconductors, Panesia also supports product development by licensing CXL 3.1 IP. It was revealed that they are currently discussing collaboration related to CXL with global companies such as Arm and HPE.

It is reported that the CXL 3.1 IP-based prototype production (Tape Out) has been completed. Panesia will be exhibiting at Booth 5 of the Santa Clara Marriott in California, USA for two days starting April 30th (local time), and will present the CXL IP interoperability verification demo there.

The interoperability verification demo consists of a procedure to verify whether the CXL device developed using the Panesia CXL IP operates properly according to the CXL standard announced by the consortium and is stably compatible with Intel/AMD CXL CPUs. This is the first challenge for a domestic startup.

Additionally, the CXL 3.1 All-in-One Framework will be showcased. The CXL 3.1 All-in-One Framework provides a CXL CPU, switch, memory expansion device, and software based on the CXL 3.1 IP.

Panesia officials explained that the CXL 3.1 all-in-one framework supports key CXL 3.1 features such as multi-level switches and memory sharing, allowing for multi-terabyte memory capacities and maximizing memory utilization.

■ Panesia CXL Interoperability Verification Demo Revealed at DevCon

Panesia will present its CXL 3.1 switch-based solution at CXL DevCon 2024, which is being held for the first time this year. CSO Mi-ryeong Kwon will be a speaker to introduce the CXL 3.1 switch technology and present related demos.

A hardware device that allows users to connect devices within a CXL 3.1 system as desired, creating a free connection relationship. The CXL 3.1 switch is designed so that the Fabric Manager software can manage internal routing rules. This allows users to easily scale their CXL systems on a large scale.

“The technology we are announcing is essential to optimizing the acceleration efficiency of big data services such as generative AI,” said Kwon Mi-ryeong, CSO. “After DevCon, we will present Panesia’s innovative technology and vision to executives from global companies such as Meta, MS, Intel, AMD, Micron, HPE, Marvel, Samsung, and Hynix at the meeting held at Meta.”

Meanwhile, Panesia is active as a member of the CXL consortium, and Intel, Nvidia, AMD, Microsoft, Meta, and IBM are also participating as members of the CXL consortium.