A next-generation semiconductor packaging technology has been developed that can increase productivity by 6.5 times and drastically reduce manufacturing costs. Overcoming the limitations of existing technology using 300mm round wafers, it has achieved high productivity and precision simultaneously with a large square panel measuring 600mm x 600mm.

The research team of Dr. Song Jun-yeop and Dr. Lee Jae-hak of the Semiconductor Equipment Research Center of the Autonomous Manufacturing Research Institute of the Korea Institute of Machinery and Materials (President Ryu Seok-hyun) under the Ministry of Science and ICT, along with Hanwha Precision Machinery Co., Ltd., Kressem Co., Ltd., MTI Co., Ltd., and Nepes Co., Ltd. have developed 14 core original technologies and patents, including FO-PLP bonding and inspection equipment and process and material technologies that can realize high-density multidimensional (2.x/3D semiconductor packaging (SIP: System In Packaging) on a large 600㎜ panel, and commercialization technologies.

FO-PLP (Fan-Out Panel Level Packaging) is a technology that implements packaging by arranging semiconductor chips on a large-area panel. Unlike the existing FO-WLP (Fan-Out Wafer Level Packaging) technology that packages at the wafer level, it uses a large-area panel, so productivity is high, but the technical difficulty is very high.

The researchers maximized productivity by using large-area 600mm x 600mm square panels rather than circular ones.

In addition, we have comprehensively developed and applied high-productivity bonding equipment (Hanwha Precision Machinery Co., Ltd.) capable of producing over 10,000 chips per hour (CPH) with a precision of ±5㎛ or less, low-residue, high-heat-resistant materials (MTI Co., Ltd.), and high-speed, large-area inspection equipment (Cressem Co., Ltd.) with a resolution of 1∼2㎛.

In the process of redistributing chips on a large-area panel, FO-PLP technology suffers from die shift errors due to differences in chip adhesive levels, rearrangement errors during the bonding process, and differences in thermal expansion coefficients between materials during molding.

As errors are amplified step by step, the final package yield decreases. The process-integrated AI inspection and correction technology developed by the Korea Institute of Machinery and Materials research team reduced chip misalignment errors in FO-PLP, thereby increasing yield and productivity.

The research team achieved a chip warpage precision of ±5㎛. This is a precision improvement of more than 30% compared to existing ones. By securing high precision through high-speed chip warpage inspection and correction technology, productivity was increased by more than 30% compared to advanced overseas companies. Productivity was improved by 6.5 times compared to existing 300㎜ FO-WLP, and package manufacturing costs were also drastically reduced. It is expected that the line width will be refined to 7㎛ or less, the world's best, and that it will be applicable to high-performance high-end packages in the future.

In relation to this, the Korea Institute of Machinery and Materials held a performance report meeting at the Ruby Hall of the El Tower in Seoul on the 26th and signed a business agreement for the commercialization of next-generation semiconductor FO-PLP technology with the Korea Semiconductor Research Association, Hanwha Precision Machinery Co., Ltd., Kressem Co., Ltd., and MTI Co., Ltd., and each organization agreed to join forces for commercialization.

Song Jun-yeop, a researcher at the Korea Institute of Machinery and Materials, said, “The FO-PLP market is a high-growth field with an average annual growth rate of 30% expected for the next five years,” adding, “FO-PLP technology is expected to lead the semiconductor packaging market, which is expected to reach 50 billion dollars in 2030.”

Meanwhile, this study was conducted as a project titled ‘Development of a high-precision FO-PLP bonding system capable of die shift error correction’ of the Materials and Components Technology Development Project of the Ministry of Trade, Industry and Energy.