Intel Foundry has unveiled a revolutionary transistor and packaging technology that improves capacitance by up to 25 percent using ruthenium (Ru) and increases throughput by 100x using a heterogeneous integration solution that enables chip-to-chip assembly processes.

Intel Foundry announced on the 9th that it participated in the IEEE International Electron Devices Meeting (IEDM) 2024 and unveiled innovative technologies for the future of the semiconductor industry.

This announcement includes new transistor and packaging technologies to meet AI demands.

Intel has improved interconnects using subtractive Ruthenium, increasing capacitance by up to 25 percent. It has also improved device performance by using silicon ribbon FET CMOS and scaled 2D FETs to facilitate GAA scaling.

Additionally, the heterogeneous integration solution enables ultra-high-speed chip-to-chip assembly, increasing throughput by 100 times. SLT (Selective Layer Transfer) enables smaller die sizes and higher aspect ratios.

Here we show the PowerVia rear power delivery enhancements and the interconnect extensions using polarizable ruthenium to overcome the limitations of copper transistors.

Intel presents a future vision of advanced packaging and transistor scaling to meet the demands of high-performance applications such as AI.

Intel continues to advance transistor scaling toward its goal of one trillion transistors.

Intel officials said, “Intel’s innovation underscores Intel’s efforts to define the semiconductor industry’s roadmap, build a global supply chain, and restore manufacturing and technology leadership in the U.S. It is expected to play a key role in leading the advancement of AI and semiconductor technology over the next 10 years.”