| Successful development of 12-layer stacking technology from existing 8-layer
| Application to HBM and utilization in AI and HPC fields


Samsung Electronics announced on the 7th that it has developed a 12-stage 3D Through Silicon Via (3D-TSV) technology.

12-level 3D-TSV is a packaging technology that connects 60,000 TSVs (transmission vias) with a diameter of several micrometers (㎛), which is 1/20 the thickness of a human hair, on the top and bottom of a semiconductor chip instead of connecting chips using gold wires.

This technology vertically stacks and connects 12 DRAM chips processed to a thickness less than half that of paper (100㎛), which can improve speed and power consumption by shortening the time it takes to send and receive signals between chips compared to existing wire bonding technology.

Samsung Electronics has maintained the same package thickness (720㎛) as the existing 8-layer HBM2 product while stacking 12 DRAM chips, enabling customers to launch next-generation, high-capacity products with higher performance without having to change the system design. In addition, by applying '12-level 3D-TSV' technology to High Bandwidth Memory (HBM), the capacity can be increased by 1.5 times by increasing the number of levels from the existing 8 to 12.

Applying 16Gb DRAM chips to 12-layer 3D-TSV technology can implement 24GB HBM products. This is a capacity that is three times* greater than the 8-layer 8GB product that Samsung Electronics is currently mass-producing.

* 8GB mass production product: 8Gb x 8 layers / 24GB development product 16Gb x 12 layers

Samsung Electronics DS Division TSP General Manager Baek Hong-joo said, “Packaging technology that can implement high performance in various fields such as AI, autonomous driving, and HPC is becoming important,” and “We will continue our ultra-gap technology leadership in the semiconductor packaging field with the 12-level 3D-TSV technology that overcomes technological limitations.”