Samsung, which had only 1% of the global foundry market share 10 years ago, has now narrowed the technology gap to the point where it can challenge the stronghold of TSMC, the number one foundry company. Samsung Electronics' foundry business division has introduced the world's first next-generation GAA-based 3nm process in just five years since its launch, showing progress that is at least one step ahead of TSMC in process miniaturization.

Samsung Electronics announced on the 30th that it has started initial mass production based on a 3-nanometer (nm) foundry process that applies GAA (Gate-All-Around) technology for the first time in the world.

The 3nm process is the most advanced technology among semiconductor manufacturing processes, and Samsung Electronics is the first in the world to introduce a 3nm process foundry service that applies the new GAA technology, a next-generation transistor structure.

Samsung Electronics' 3nm GAA first-generation process achieved △45% power reduction, △23% performance improvement, and △16% area reduction compared to the existing 5nm FinFET process.

In addition, Samsung announced that the second-generation GAA process is also in the process of development and testing, with the goal of mass production in 2023. The second generation of GAA is expected to achieve performance improvements of △50% power reduction, △30% performance improvement, and △35% area reduction.

Samsung Electronics explained that following the initial production of high-performance computing (HPC) system semiconductors using the 3nm process, it plans to expand into mobile SoCs, etc.

Choi Si-young, head of Samsung Electronics Foundry Business Division, said, “Samsung Electronics has grown rapidly by being the first in the foundry industry to preemptively introduce new technologies such as High-K Metal Gate, FinFET, and EUV, and now we are the first in the world to provide foundry services for a 3nm process using MBCFET GAA technology.” He added, “We will continue to actively develop differentiated technologies and build a system that rapidly increases process maturity.”

■ Samsung’s cutting-edge MBCFET GAA proprietary technology
Samsung Electronics has applied the next-generation GAA technology for the first time in the world, in which gates surround the four sides of the channel through which current flows in the transistors that make up semiconductors.

Unlike the existing FinFET structure that wraps around three sides of the channel, GAA technology is considered a next-generation semiconductor core technology that overcomes the degradation of transistor performance due to process miniaturization by increasing the gate area and increases data processing speed and power efficiency.

In addition, Samsung Electronics is making the channel thinner We also applied our unique MBCFET GAA structure implemented in the form of a wide nanosheet.

By adjusting the width of the nanosheet, the channel size can also be varied. Since the existing FinFET structure cannot adjust the height of the fin surrounding the gate, the channel size could be increased by increasing the number of fins in the horizontal direction. This was only possible to adjust the continuous channel size, but the MBCFET technology applied to the 3nm mass production this time is a nanosheet structure, so the sheet width can be increased flexibly, and various channel sizes are possible through this.

In addition, it has a great advantage in designing high-performance, low-power semiconductors because it can control current more finely than the existing FinFET structure or the general nanowire GAA structure. This has improved the On-Off characteristics through a structure that uses four sides as channels, and through this, just like a faucet's function has improved so that water does not leak even when slightly turned off, the transistor operates appropriately even at low voltages, resulting in lower operating voltage and higher power efficiency.

■ Maximized PPA implementation through design process technology optimization
Samsung Electronics has been working to maximize PPA (Power: Power Consumption, Performance: Performance, Area: Area) through 3nm design process technology co-optimization (DTCO) along with the application of the nanosheet GAA structure.

Samsung Electronics' 3nm GAA 1st generation process achieved △45% power reduction, △23% performance improvement, and △16% area reduction compared to the existing 5nm FinFET process, and the GAA 2nd generation, scheduled for mass production next year, is expected to have △50% power reduction, △30% performance improvement, and △35% area reduction.

Samsung Electronics said, “We plan to lead the next-generation foundry service market by providing PPA optimized for customer needs and maximized power-to-performance ratio (performance per unit of power) in the future.”

Samsung Electronics is providing semiconductor design infrastructure and services based on the 3nm process together with SAFE (Samsung Advanced Foundry Ecosystem) partners such as Synopsys and Cadence, thereby creating a 3nm semiconductor ecosystem. It's expanding.

“Our GAA-based 3nm collaboration with Samsung will continue to expand across Synopsys’ digital design, analog design, and IP offerings to deliver differentiated SoCs for key high-performance computing applications,” said Sankar Krishnamoorthi, general manager of Synopsys’ Silicon Realization Group.

“Cadence is working with Samsung Electronics to provide services that can increase productivity in circuit design and simulation with automated layout,” said Tom Beckley, vice president and general manager of Cadence’s Custom IC & PCB Group.