The world's population is about 7.7 billion, but the number of devices in use exceeds 500 billion. According to Cisco Global Cloud Index data, unlike before the 2000s when the per capita PC and mobile phone penetration rate was minimal, the number of devices has exceeded the population since 2008, with the average number of devices per person estimated at 15, and the number of devices projected to reach 1.25 trillion by 2030.

The semiconductor trend has been doubling performance every two years based on Moore's Law, but has reached a technological limit and is now facing innovation barriers such as cost issues and micro-process limitations. At this point, various development methods are being explored for the development of next-generation technologies.

At the Summer Conference of the Korean Institute of Electromagnetic Engineering and Science, Moon Seong-wook, Master of Samsung Electronics Foundry Business Division, gave a keynote speech on the topic of ‘Power & Signal Integrity Technology Challenge for Implementing 2.5D·3D Semiconductor Design.’ The in-depth presentation on Samsung's packaging technology and solutions to power and signal integrity issues drew a steady stream of visitors.

■ Heterogeneous Packaging Trend, Power/Signal Integrity Required

One of the reasons for the emergence of heterogeneous integration in semiconductors is the cost issue. By combining multiple chiplets as building blocks to produce a single processor, the yield can be increased and the cost can be reduced, so many semiconductor manufacturers have adopted this.

The more advanced the node process, the higher the unit cost and the lower the yield, so the larger the die, the greater the possibility of defects, and the greater the resulting losses. That is why heterogeneous packaging in the building block method, which minimizes die size by designing only the necessary chiplets in advanced node processes, is the one that can satisfy both yield and performance.

“Morally, integrity is the absence of defects, but in semiconductor design, integrity is not defined as the absence of defects, but as designing so that even if there are defects, they do not affect power or signals.”

Master Moon Sung-wook defined semiconductor power and signal integrity, emphasizing that it is a field that requires meticulous design down to the smallest detail.

Integrity must be examined in a diverse and complex manner, including between systems, between transistors, and between modules. In terms of power, issues include voltage drop, switching noise, and crosstalk. In terms of signals, issues include attenuation characteristics, radio wave reflection, dispersion, interference, and crosstalk.

■ 2.5D·3D Semiconductor Challenges and Future

Master Moon Sung-wook mentioned the 2.5D silicon interposer, saying, “Just a few years ago, the die size was limited to 1000mm² (square millimeters), but recently, with HBM starting to be implemented in 8 or 12, the size is growing to the point where we will need to prepare for 2400mm² or 3200mm² in the future.” This requires kilowatt-class power in data centers.

These power issues have led to a focus on design implementations that use 'decap (decoupling capacitor)' solutions, and solving heat generation issues is also a major concern for packaging engineers, Moon added.

Technical challenges in high-performance computing (HPC) include: △Increasing die size and reducing Turn Around Time (TAT) to implement high performance, △High thermal density, △Yield issues and rapid yield increase due to increasing die size, △Requirements for wide coverage and short TAT due to increased test processes, and △Multi-die PSI analysis, which remain as tasks to be solved in the future.

3D integrated circuits (ICs) can be used in both HPC and mobile, and have cost-saving advantages. 3D ICs can also have advantages in terms of performance and form factor. In addition, Master Moon pointed out that there are many technical challenges, and the part surrounding the technical challenges in 3D semiconductors is TSV (Through Silicon Via).

Samsung Foundry is taking the lead in creating an ecosystem for MDI (Multi Die Integration) packaging. It is developing related tools with EDA companies such as Synopsys, Siemens, and Ansys. △With Synopsys, it is collaborating on an early-stage noise prevention PSI design solution, △With Ansys, it is collaborating on a large DB capacity PI/SI solution, and △With Siemens, it is collaborating on physical verification and Thermal/Stress solutions. Moon Master diagnosed that “since the 2.5D/3D packaging area is not popular across the global industry, tools are not developing quickly in the EDA industry.”

Moon Master said, “The semiconductor trend is expected to greatly increase in the 2.5D and 3D areas,” and “A lot of preparation will be needed amidst the current infrastructure concerns.” Samsung Electronics emphasized that it is preparing ahead of time for the expansion of the 2.5D and 3D areas and is already implementing them through some customers.