최근 첨단 반도체 파운드리 공정에서 1~2나노 차세대 기술 로드맵을 발표하며 초미세 패터닝에서 옹스트롬 시대가 열렸다. 인텔이 1.8나노에 해당하는 18옹스트롬 기반 로드맵을 본격화하는 가운데 이를 뒷받침하는 소재·장비사 기술 혁신 또한 발빠르게 기술 한계를 뛰어넘고 있다.

▲Park Gwang-seon, CEO of Applied Materials Korea
Patterning cost reduced by eliminating bridge defects
EUV line edge roughness must be resolved
Patterning effective market size ↑$8 billion
The recent announcement of a 1-2nm next-generation technology roadmap in advanced semiconductor foundry processes has ushered in the angstrom era in ultra-fine patterning. As Intel is fully implementing its 18 Angstrom-based roadmap corresponding to 1.8 nanometers, the material and equipment technology innovations supporting it are also quickly overcoming technological limitations.
Applied Materials held a media briefing at its Korean branch office located in Bundang, Seongnam-si, Gyeonggi-do on the 4th.
The briefing revealed Applied Materials' expanded portfolio of patterning solutions for Angstrom-era chip manufacturing, introducing Sculpta, Sym3 Y Magnum, Aselta, and Producer XP Pioneer CVD.
Applied Materials forecasts $200 million in sales this year and $500 million in 2025 with solutions that improve process efficiency and reduce defects related to EUV and high-NA EUV lithography through a new etching system that did not exist before.
Park Kwang-sun, CEO of Applied Materials Korea, said, “In order to better implement EUV, which implements ultra-fine patterning, several technologies are needed.” He added, “Many of Applied’s technologies related to patterning have been prepared through ecosystem collaboration for over 10 years, and as a result of such collaboration, we will provide our customers with a roadmap and cost reduction through this new etching technology.”
■ Sculpta, patterning cost ↓ by eliminating bridge defects 
▲Patterning process flow (Source: Applied)
Last year, Applied Materials announced the Centura Sculpta patterning system, which reduces the number of EUV double patterning steps and allows for tighter tip spacing compared to single EUV or high-NA EUV exposure.
Currently, Sculpta equipment is said to be applied to leading edge customers around the world and related applications are being expanded, it explained. The advantage of adopting Sculpta is not only that it reduces tip spacing, but also that semiconductor manufacturers can reduce patterning costs and improve chip yield by eliminating bridge defects.
Intel announced that it had introduced the Sculpta system for the Angstrom process, and that it had improved throughput, wafer yield, and cost. Samsung Electronics is known to be evaluating the introduction of the Sculpta system to its 4nm process.
“It is difficult to properly transfer a pattern onto a wafer, and the challenge facing EUV lithography is the occurrence of ‘stochastic’ defects,” said Gil-Yong Lee, head of technology marketing and strategy programs at Applied Materials. “These random variations form bridges between line edge roughness and metal lines, leading to various defects.”
■ EUV line edge roughness must be resolved 
▲ Lee Gil-yong, Head of Technology Marketing and Strategy Programs at Applied Materials (Photo: Applied)
If the line edge roughness is large, the electronic resistance increases, and if the rough line edge is etched into the wafer, an open circuit or short circuit may be formed. This type of defect is occurring more frequently these days as manufacturers are narrowing the gap between lines and patterns.
Applied is introducing the Sim3 Y Magnum etch system, which supports both deposition and etching in the same chamber, to deposit materials on rough edges and smooth EUV line patterns, thereby increasing yields and reducing line resistance.
Currently, SIM3W Magnum is adopted by major semiconductor manufacturers for foundry logic and is also the most widely adopted etching technology for DRAM EUV patterning.
In addition, it is reported that the pattern uniformity can be optimized when combining the Producer XP Pioneer CVD patterning film. The Pioneer film has a specification of thinner thickness than existing ones while having excellent sidewall pattern shape uniformity based on high-density carbon with high elasticity against etching chemicals used in advanced processes.
Major memory manufacturers are adopting Pioneer for DRAM patterning. It is reported that Pioneer is increasing the options for patterning optimization in combination with Sculpta and Sim3 Wi Magnum.
■ Angstrom-era metrology, fine alignment support Another challenge in the microprocessing is to precisely define and place billions of features on each layer. In the patterning process consisting of multiple layers, precise alignment with the next layer is critical, and even small placement errors can have a significant impact on chip performance and even cause defects that adversely affect yield.
Applied is leading the way in logic and memory EUV patterning solutions with its electron beam metrology systems. The company announced that it has acquired Aselta Nanographics, a design-based metrology technology company, and emphasized that it will be able to collect several times more data about the shapes each recipe creates on patterned films and wafers through contouring.
The company explained that Acelta Contour technology is now integrated into electron beam metrology systems such as the Applied Verity SEM, providing semiconductor manufacturers with end-to-end capabilities to solve a wide range of metrology problems, including ultra-fine processes.
Meanwhile, according to Applied Materials, the effective patterning market size has grown from $1.5 billion 10 years ago to over $8 billion today, including four types of material removal: CVD, ALD, etching and selective removal, thermal processes, and electron beam metrology.