Nepes is aggressively targeting the inference AI field, which has high market growth potential, with its new 8-layer RDL interposer technology.

Nepes announced that it presented its fan-out based RDL interposer technology at the 74th Electronic Components Technology Conference (ECTC) held in Denver, Colorado, USA from May 28th to 31st (local time).

On the 29th, the second day of the event, Nepes shared the current status of advanced packaging technology with a paper titled ‘Single and Multi NPU Chiplet Heterogeneous Integration Packaging Based on Fan-Out RDL Interposer With Silicon Bridge Technology’ at the Thermo-mechanical Stress and Reliability Analysis for Materials in Future Packaging session.

The technology is characterized by implementing chiplet packaging, which vertically and horizontally connects multiple chips on an interposer, with a fan-out process-based redistribution (RDL) interposer instead of a silicon (Si) interposer.
/> As demand for artificial intelligence semiconductors increases, chiplet packaging technology has become a major topic, receiving great attention from field participants due to its advantages such as excellent electrical characteristics, production efficiency, and reduced manufacturing costs.

In particular, at this ECTC, in a situation where 6-layer RDL interposer technology is common worldwide, an 8-layer RDL interposer technology was developed and shared, which is two more layers stacked than before.

This is significant in that it has changed from a structure that previously required a substrate to a structure that does not require a substrate.

In other words, in the existing case, after the RDL interposer manufacturing process and chip bonding and molding processes, an additional flip chip process must be performed on the substrate.

On the other hand, the 8-layer process eliminates the need for a flip-chip process on the substrate, enabling packaging without a separate substrate, thereby reducing the overall package size. In addition, the process is simplified, increasing process efficiency, and simplifying the electrical connection with the complex substrate enables the implementation of excellent electrical characteristics.

A Nepes official said, “The RDL interposer is a suitable solution for connecting various chips and is expected to be widely used in areas with high market growth potential, such as edge computing for inference artificial intelligence,” adding, “We plan to actively pursue commercialization through network reinforcement and technology cooperation with customers in the future to secure global semiconductor package competitiveness.”