Implementation Method for OpenCV Application on Zynq-7000 All Programmable SoC using Vivado HLS with HW Acceleration

This web seminar will discuss how to implement real-time computer vision algorithms using hardware acceleration and how to integrate them into your custom designs using Xilinx Zynq® 7000 All Programmable SoC devices. Through step-by-step examples, we will demonstrate how to accelerate custom video algorithms and implement them by leveraging the HLS (High-Level Synthesis) video library that guarantees synthesis of OpenCV library functions and your custom video algorithms, the Vivado® HLS compiler, and the Vivado IP Integrator to implement them on FPGA fabric within your embedded design. This design flow enables the implementation of real-time embedded computer vision algorithms through a seamless combination of high-performance, low-power on-chip programmable hardware for pixel processing on high data rate images such as FullHD or UHD, and a software-programmable ARM processor core for frame processing tasks operating at lower data rates. What participants will learn: 1. Xilinx Smarter Vision solutions for computer vision. 2. How to implement OpenCV functions using the Zynq-7000 All Programmable SoC. 3. How to replace software-implemented OpenCV function calls with hardware-accelerated functions that operate up to 700 times faster using HLS. 4. How to implement hardware accelerators with standard AXI4 interface for OpenCV functions and easily connect them to the overall system. 5. How to integrate hardware accelerator designs generated by Vivado HLS into a reference design based on the Zynq-7000 All Programmable SoC ZC702 evaluation board using Vivado IP Integrator.