RISC-V Parallel Processing Synchronization and Locking Techniques

This webinar is a technical seminar sponsored by Mouser. 

In this webinar, we have prepared a session to share information on RISC-V parallel processing synchronization and locking techniques.

RISC-V is a 64-bit microprocessor that has recently emerged as a rising technology.
With a very efficiently designed instruction set architecture (ISA), it overcomes the shortcomings of x86, ARM, and MIPS, operating very efficiently at low power consumption.
Furthermore, by opening its internal technology, it shares numerous technical resources so that anyone can conduct research and development without licensing fees.

Since we have already conducted a webinar on the RISC-V instruction set architecture (ISA), we believe you are already well acquainted with the advantages of RISC-V.

In this webinar, we will specifically address synchronization and locking techniques, which are issues that must be resolved in microprocessor parallel processing.
RISC-V supports instructions that enable more efficient synchronization and locking processing.
- Load Reserved
- Store Conditional
- AMO series instructions
- FENCE synchronization

In this webinar, we have prepared a session to gain a detailed understanding of the above instructions.
If you have taken considerable interest in synchronization and locking techniques thus far, we hope this webinar will be a valuable opportunity for you to understand them clearly.