Fast and Powerful Verification Productivity Increase - Achieving Coverage Closure Using Questa inFact

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This webinar introduces the Questa inFact solution, which optimizes stimulus generated in existing SystemVerilog/UVM constrained random test environments to achieve coverage closure more rapidly.

Questa inFact is a graph-based verification tool that generates test stimulus during functional verification of digital hardware design, and recently provides an App that can utilize the emerging Portable Test and Stimulus (PSS).
Test scenario modeling through PSS helps users focus on high verification requirements for what needs to be tested, and enables the creation of valid specific tests through automation. Moreover, it makes these tests usable in various verification environments. Wouldn't it be nice to have a verification environment where you can focus more on what to test rather than worrying about how to conduct tests in existing SystemVerilog/UVM verification environments?

To configure such a verification environment, the most straightforward approach would be to add tests created using PSS to existing SystemVerilog/UVM testbenches, but there is an easier way. The inFact PSS App for SystemVerilog provides a verification environment that allows users to focus more on the target they want to test rather than how to test it. By reading and utilizing existing SystemVerilog classes and covergroups through the inFact PSS App, you can maximize the utilization of existing testbenches while also enhancing verification productivity.
Through this webinar, you will be able to see how inFact PSS App generates more accurate SystemVerilog covergroups, pre-analyzes constraints before simulation, and how efficient and non-repetitive stimulus generation aids in coverage closure and bug hunting.

We hope your participation in the Questa inFact webinar will be a valuable experience. Thank you.