HLS 101 - What Every RTL Hardware Design Team Should Know

High-level synthesis refers to the synthesis of algorithm designs described in high-abstraction-level languages such as C/C++/SystemC into RTL hardware.

In recent application areas such as computer vision, artificial intelligence machine learning, and 5G communications, considerably complex algorithms are required.
When implementing algorithms requiring such complex computations into actual hardware using the conventional manual hardware coding method, the development period becomes significantly extended. This causes delays in product launch timing and reduces profits for the development team. Additionally, in the case of image processing using deep learning, which has recently gained attention, a large number of arithmetic operations and memory accesses are required. Architecting tens of thousands or hundreds of thousands of operations and memory accesses in hardware and manually coding them for hardware design would be an extremely difficult task.

 

The Catapult HLS solution implements RTL by taking high-level languages such as C++/SystemC as input. Designers input synthesizable designs and apply hardware constraints such as operating frequency, clock, reset, and the type of memory to be used to the tool.
To satisfy latency and throughput design specifications, architecturing such as pipelining and loop unrolling is performed as tool options. In this way, Catapult enables the implementation of optimized hardware RTL according to designer constraints. Furthermore, HLS extends the existing design flow and provides a new and powerful approach to hardware design.

In fact, Catapult HLS is most useful for RTL engineers currently developing SoC IPs. It is commonly a great misconception that if RTL hardware is created using high-level languages such as C++/SystemC, future RTL engineers will lose their jobs.
However, the reality is quite different. Although the abstraction level of the design language is higher, the hardware structural analysis and understanding accumulated through long RTL development experience achieves significantly superior optimization levels when utilizing HLS.

 

Suppose there is a design where an arithmetic block repeatedly requires reading and writing memory within multiple nested loops followed by complex computations. In this case, if HLS design is performed considering hardware memory architecture, the design specification can be satisfied with less memory. Otherwise, unnecessary additional memory will be used, increasing the overall cost regarding chip size. Additionally, as the design is described in a higher-level language, the design period is shortened, and the time invested in verification can be increased accordingly, enabling the creation of more refined hardware designs.

We hope you will attend the webinar together with Mentor Siemens Business's Catapult solution, which is leading in the HLS field, for a beneficial experience.