2.5D Integration, the Key to Solving Advanced Semiconductor Yield Problems
Intel Foveros and TSMC CoWoS technologies are representative examples.
When advanced wafer-level packaging processes are needed


As the importance of AI technology increases in all industries, interest in AI semiconductors that specialize in AI processes is heating up. On the 10th of this month, our government also announced that it would invest 1.96 trillion won over 10 years in AI semiconductor development. This is the largest R&D project conducted in the past five years.

Designing and producing cutting-edge AI semiconductors, among various semiconductors, is not an easy task.

According to IBS, a U.S. consulting firm, the typical semiconductor design cost is $51.3 million for a 28nm planar device. The cost increases to $297.8 million for 7nm and $542.2 million for 5nm. For 3nm, it ranges from a minimum of $500 million to a maximum of $1.5 billion.

Even if a huge amount of money is invested to design a semiconductor, the only foundries that can produce it with a reasonable yield are TSMC in Taiwan, Samsung Electronics in Korea, and Intel in the US. They too invest astronomical amounts of money every year to maintain and increase yields.

According to Choi Kwang-seong, a senior researcher at the Electronics and Telecommunications Research Institute (ETRI), 2.5D integration technology and 3D integration technology were designed to solve the yield problem of advanced semiconductors including AI semiconductors, through 'Development Trends of 2.5D/3D Integration Technology for AI Modules.'

2.5D integration technology is a technology that increases integration by flipping the device onto a silicon interposer with through silicon vias (TSVs), i.e., flip chip bonding.

3D integration technology is a technology that forms TSVs in the device itself and integrates them in three dimensions. Currently, Samsung Electronics and SK Hynix are applying this technology to mass produce HBM (High Bandwidth Memory).


◇ 2.5D integration, the most realistic way to increase semiconductor yield

Researcher Kwang-Seong Choi introduced the related content, saying that the correlation between 2.5D integration technology and advanced semiconductor process yield was proven in 2012 when TSMC began mass producing Xilinx's FPGA using 2.5D integration technology.

At that time, FPGAs were manufactured using 28nm technology. The problem was yield, and the cause of the yield decrease was the large chip size. To solve this, a method of separating chips emerged. One chip was separated into four pieces.

A new component, a silicon interposer, was needed to make the separate chips operate as a single chip. This is because the number of bumps for bonding the separated individual chips to the substrate was approximately 50,000, the pitch was approximately 45㎛, and the minimum width of the wiring for connecting these bumps was very thin at 0.5㎛.

“The silicon interposer employed in 2.5D integration technology offers a realistic way to physically connect high-performance chips with high-density bumps to a substrate,” said Choi. “This technological transition offers a solution that still works to address the cost issues that arise as semiconductor process nodes become smaller.”

An example of this is chiplet integration technology, which manufactures unit IP blocks called chiplets at various semiconductor process nodes and integrates them onto a silicon interposer to reduce overall costs.


◇ Intel increases yield through wafer-level integration process

In June 2020, Intel introduced to the market a laptop CPU codenamed 'Lakefield' developed with a packaging technology called 'Foveros'. Intel says the processor delivers 12 percent higher performance, 92 percent lower standby power, and 24 percent higher overall power efficiency than previous-generation processors using a single chip.

Foveros is a 3D packaging technology that completes a logic wafer and then forms TSVs. After that, devices from various semiconductor process nodes are bonded through the C2W (chip-to-wafer) process, and a wafer-level molding process is performed, and the upper surface of the bonded chips is exposed through a grinding process to establish heat dissipation measures.

Next, the logic wafer’s underside is ground and polished to expose the TSVs and form the back-end interconnects and solder bumps. Finally, the wafer is separated into individual chips, which are then integrated onto a substrate with HBM and other components to complete the Lakefield processor.

Researcher Choi explained that this process is differentiated from existing packaging processes in several aspects.

First, the mixing of packaging technology and fab process. Previously, fab process and packaging process could be clearly divided into pre-process and post-process. However, in Foveros, TSV formation process, bonding process, and molding process are mixed, making the distinction between fab process and packaging process meaningless.

Second, expensive logic wafers are used as substrates. Third, all processes are carried out at the wafer level.


◇ 2.5D integration, overcoming fear of wafer-level defects

Researcher Choi said that 2.5D integration technology for system semiconductors originated from TSMC. The concept of TSMC's CoWoS (Chip-on-Wafer-on-Substrate) technology is similar to Intel's Foveros technology.

However, it differs in that it uses a TSV silicon interposer as a substrate rather than a device such as logic. Other processes such as C2W bonding, wafer-level molding, and TSV exposure through silicon grinding and polishing are technologies already introduced by CoWoS.

Researcher Choi said, “Even now, one of the most difficult processes in manufacturing TSV silicon interposers at the time was handling the 300mm diameter, 100㎛ thick TSV silicon interposers during the process or while moving between processes.” This is because they break easily.

To solve this problem, material and process companies around the world have proposed various technologies. TSMC solved it by increasing the thickness of the TSV silicon interposer it wanted to handle, and by applying bonding and molding technologies, which are part of the packaging process. This idea could be implemented because it overcame the fear of loss in case of wafer-level defects.

Researcher Choi pointed out that although there have been many attempts at advanced wafer-level packaging processes in Korea, there is still a prevailing atmosphere of difficulty in applying them due to the fixed idea that if a defect occurs in even one process, there is a high risk of it occurring in large quantities, and the loss of discarding expensive devices will be too great.

Meanwhile, domestic foundries still criticized, “The fixed idea that semiconductor processes are divided into front-end and back-end processes, and that most of the added value comes from the front-end process, so the back-end process only needs to increase yield, is preventing wafer-level processes from being implemented domestically.”


◇ Disruptive innovation beyond existing packaging technology is needed

The core component of AI modules, 3D stacked memory, or HBM, is mainly manufactured by domestic companies Samsung Electronics and SK Hynix. The two companies’ HBMs are manufactured through the following process.

First, the memory device is made, then the TSV is formed, and then the BEOL (Back End Of Line), redistribution, and bumps are made. After that, temporary bonding is made to the carrier wafer, the TSV is exposed, and the back redistribution and bumps are made. This wafer is separated from the carrier wafer and then a stacking process is performed on the master memory.

What is different from Intel's Foveros and TSMC's CoWos is that the master memory is a semi-finished product with TSV completed. The thickness of the master memory is only about 50㎛, so it is temporarily bonded to the carrier wafer. Researcher Choi pointed out that the HBM manufacturing process is divided into the traditional pre-process and post-process.

Researcher Choi said, “In order for our country’s system semiconductor industry to overcome TSMC and Intel, a disruptive innovation that negates the perspective on existing packaging technology is needed,” and advised, “We need to change the perspective of packaging technology from a post-process after the semiconductor front-end process to an innovative technology that creates new added value and satisfies market demands.”