HBM 기술력에서 시장 리더십을 차지한 SK하이닉스가 차세대 HBM4에서 TSMC의 첨단 패키징 역량을 더해 고객사 제품 양산에 나설 것으로 보인다.
▲SK Hynix HBM3E product photo (Photo: SK Hynix)
MOU signed for cooperation on HBM4 development and next-generation packaging technology
TSMC Foundry Utilization, Customer-Foundry-Memory Triangle Solidarity
SK Hynix, which has achieved market leadership in HBM technology, is expected to mass produce customer products by adding TSMC's advanced packaging capabilities to the next-generation HBM4.
SK Hynix announced on the 19th that it has decided to work closely with Taiwanese foundry company TSMC to strengthen its next-generation HBM production and advanced packaging technology capabilities.
SK Hynix recently signed a memorandum of understanding (MOU) for technological cooperation with TSMC in Taipei, Taiwan, and plans to jointly develop HBM4 (6th generation HBM), which is scheduled for mass production in 2026.
First, we will improve the performance of the Base Die, which is mounted at the bottom of the HBM package. HBM is made by stacking the Core Die, which is a single DRAM chip, on top of the Base Die and vertically connecting them using TSV technology. The Base Die is connected to the GPU and plays a role in controlling the HBM.
SK Hynix has been producing base dies using its own process up to the 5th generation HBM3E, but plans to use a logic-edge process starting with HBM4. This is because applying an ultra-fine process to produce this die allows for the addition of various functions. This is expected to enable the production of customized HBM that meets the broad market demands, including performance and power efficiency.
SK Hynix emphasized, “As a global leader in AI memory, we will lead another HBM technology innovation by joining forces with TSMC, the number one foundry company,” and “We will overcome the limits of memory performance based on three-way technology collaboration between customers, foundries, and memory.”
In addition, they decided to cooperate to optimize the combination of SK Hynix's HBM and TSMC's CoWoS technology and jointly respond to customer requests related to HBM.
CoWoS (Chip on Wafer on Substrate) technology is a unique process patented by TSMC, a packaging method that connects logic chips, GPU/xPU, and HBM on a special substrate called an interposer. It is also called 2.5D packaging because the logic chip and the vertically stacked (3D) HBM are combined into one on a horizontal (2D) substrate.
SK Hynix President Kim Joo-sun said, “Through collaboration with TSMC, we will not only develop the highest-performance HBM4, but also accelerate open collaboration with global customers,” adding, “Going forward, we will strengthen our competitiveness in customer-tailored memory platforms and solidify our position as a ‘total AI memory provider.’”
“TSMC and SK hynix have maintained a strong partnership for many years, delivering the world’s best AI solutions to the market by combining cutting-edge logic chips with HBM,” said Kevin Zhang, senior vice president and co-deputy chief operating officer of TSMC. “With HBM4, we will continue to work closely together to deliver the best integrated products that will be key to our customers’ AI-driven innovations.”