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Increasing Horizontal Density of Cell Arrays
Across Wafers with Second-Generation
Multi-tier Memory Hole Technology
Full-Scale Commercial Production in H2 2020
Western Digital (WD) announced on the 4th that it has successfully developed BiCS5, fifth-generation 3D NAND technology.
BiCS5, based on TLC and QLC technology, addresses the increasing volume of data related to connected cars, mobile devices, and AI.
WD has begun initial production of 512 gigabit (Gb) BiCS5 TLC chips. Full-scale commercial production of BiCS5 is expected to commence in H2 2020. BiCS5 TLC and BiCS5 QLC will be offered in various capacities including 1.33 terabit (Tb).
BiCS5 is the highest-density, most advanced 3D NAND technology developed by WD to date. Through second-generation multi-tier memory hole technology and improved engineering processes, as well as enhancements to 3D NAND cells, it significantly increases the horizontal density of cell arrays across wafers.
By combining this lateral scaling technology with 112-layer vertical memory technology, BiCS5 can store 40% more bits per wafer compared to WD's 96-layer BiCS4 technology. Performance is also enhanced, with BiCS5 delivering 50% faster input/output (I/O) performance compared to BiCS4.
Across Wafers with Second-Generation
Multi-tier Memory Hole Technology
Full-Scale Commercial Production in H2 2020
Western Digital (WD) announced on the 4th that it has successfully developed BiCS5, fifth-generation 3D NAND technology.
▲WD, BiCS5 3D NAND Technology Development (Image=WD)
BiCS5, based on TLC and QLC technology, addresses the increasing volume of data related to connected cars, mobile devices, and AI.
WD has begun initial production of 512 gigabit (Gb) BiCS5 TLC chips. Full-scale commercial production of BiCS5 is expected to commence in H2 2020. BiCS5 TLC and BiCS5 QLC will be offered in various capacities including 1.33 terabit (Tb).
BiCS5 is the highest-density, most advanced 3D NAND technology developed by WD to date. Through second-generation multi-tier memory hole technology and improved engineering processes, as well as enhancements to 3D NAND cells, it significantly increases the horizontal density of cell arrays across wafers.
By combining this lateral scaling technology with 112-layer vertical memory technology, BiCS5 can store 40% more bits per wafer compared to WD's 96-layer BiCS4 technology. Performance is also enhanced, with BiCS5 delivering 50% faster input/output (I/O) performance compared to BiCS4.
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