Automation for Coherent and Non-Coherent Subsystems

Arteris announced its next-generation interconnect timing automation solution, the "PIANO 2.0 Timing Closer Package."

PIANO 2.0 provides automated interconnect timing closure for both cache coherent and non-coherent subsystems for customers using the FlexNoC Physical package.

On-chip interconnect has become the most critical factor in timing closure issues. These issues are typically discovered late in the design process, causing schedule delays or product launch postponements.



PIANO 2.0 addresses backend timing issues by employing technology that operates from the early stages of the SoC design flow, reducing the risk of schedule delays. This new technology provides customers using Arteris's FlexNoC and Ncore interconnect products with an understanding of physical interconnect distance concepts.

First, PIANO calculates the length of individual interconnect links and traces, then automatically connects the interconnect pipeline at tight timing by leveraging semiconductor process technology information and performance targets. Subsequently, PIANO supports evaluation of this timing closure circuit by utilizing the physical synthesis capabilities of Synopsys or Cadence tool chains.

K. Charles Janac, Chairman and CEO of Arteris, stated, "The core technology of the PIANO Timing Closer Package is currently being applied to several complex FinFET SoC designs in production," and added, "PIANO 2.0 is the result of 18 months of collaboration with industry-leading semiconductor design teams to deliver a next-generation automatic interconnect timing closer solution that works with both Arteris's Ncore cache coherent interconnect and FlexNoC non-coherent interconnect IP products."