Expanding support for 7nm FinFET Plus and 12nm FinFET process technologies

Mentor, a Siemens business, announced that its Mentor Calibre nmPlatform and Analog FastSPICE (AFS) Platform have been certified for TSMC's 12nm FinFET Compact Technology (12FFC) and the latest version of 7nm FinFET Plus processes. The Nitro-SoC™ place and route system has also been certified to support TSMC's 12FFC process technology.

“TSMC is pleased to be working closely with Mentor, who continues to increase its value to the TSMC ecosystem by providing a broader range of capabilities to their tool flow in support of our new 12nm and 7nm FinFET Plus processes,” said Suk Lee, senior director of Design Infrastructure Marketing at TSMC. “Mentor has been a long-standing strategic partner, and with Siemens’ aggressively increasing investment in Mentor’s electronic design automation (EDA) technologies, we anticipate that together we will be able to help our mutual customers bring new and even more exciting IC innovations to market.”

Mentor has enhanced its Calibre nmDRC and Calibre nmLVS tools for TSMC's latest 12nm and 7nm FinFET Plus processes. Working with TSMC, Mentor not only ensured adequate coverage but also optimized the design kit for runtime performance. Additionally, TSMC and Mentor have collaborated to ensure that extreme ultraviolet (EUV) lithography requirements are recognized by their joint customers within Calibre design rule checking (DRC) and multi-patterning software.

Not only has the Calibre YieldEnhancer tool been certified for TSMC's 12nm and 7nm FinFET Plus processes, but Mentor and TSMC are also jointly implementing an enhanced use model that optimizes fill runtime, minimizes fill layer changes through Electrical Change Order (ECO) fills, and ensures consistency across the entire hierarchy using a 'fill-as-you-go' methodology.

The Calibre PERC reliability platform is a verification solution for IP and full-chip reliability analysis. Random path resistance calculations and current density reliability checks are critical for today's complex and dense chip designs. However, scalability is required to complete these checks on ultra-large 12nm and 7nm FinFET Plus designs. TSMC and Mentor have collaborated to enable the Calibre PERC solution to leverage new multi-CPU execution capabilities, enabling mutual customers to more quickly identify and resolve full-chip reliability issues in their designs.

The AFS platform, including the AFS Mega circuit simulator, is certified for TSMC's 12nm and 7nm FinFET Plus processes. The AFS platform supports all the features required for TSMC's design platforms for mobile and HPC applications. Analog, mixed-signal, and RF design teams at leading global semiconductor companies are benefiting from the AFS platform to verify their chips, designed with TSMC's latest technologies.

Mentor's Nitro-SoC™ place and route system is certified for TSMC's 12nm process. In addition to supporting the 12nm process rules, Mentor has enhanced the core engines of Nitro-SoC to meet the new standard cell architecture requirements and design rules for this high-density, power-efficient process. This enables Mentor to deliver a digital implementation flow for the 12nm node.

“Mentor is excited to become a key element of TSMC’s ecosystem,” said Joe Sawicki, vice president and general manager of Mentor’s Design to Silicon business unit. “The solutions TSMC and Mentor are delivering together this year will continue to provide our mutual customers with multiple design avenues to deliver IC innovations for the mobile, high-performance computing, automotive, and IoT/wearables markets.”