Technology that achieves higher integration capacity than traditional methods

Mentor, a Siemens business, announced that it has enhanced its Calibre® nmPlatform, Analog FastSPICE™ (AFS™) Platform, Xpedition® Package Integrator, and Xpedition Package Designer tools to support TSMC's innovative InFO integrated fan-out advanced packaging and CoWoS (chip-on-wafer-on-substrate) packaging technologies.

Customers can achieve higher levels of integration and capacity than traditional one-dimensional ICs by mixing multiple silicon dies in a single device through TSMC’s InFO and CoWoS 3D packaging technologies.

Mentor is currently marketing a complete InFO verification and analysis suite from design to package, based on the Mentor Calibre and Xpedition platforms. Key benefits include a rapid design-to-tape-out flow powered by the Xpedition Package Integrator's rapid hierarchical design prototyping environment, which is integrated into the Xpedition Package Designer and Calibre sign-off verification suite. Through additional collaboration, cross-probing capabilities between Calibre 3DSTACK and Xpedition tools have been extended, and the results can be viewed within the Calibre RVE interface.

TSMC and Mentor have also enabled Mentor's thermal analysis products (including Mentor AFS and Calibre xACT™ products) to support thermal awareness simulations for customers' InFO designs.

Mentor enabled InFO and CoWoS designers to verify timing requirements by enhancing Xpedition Package Integrator to support netlisting capabilities integrated with Calibre xACT extraction results to realize package-level cross-die timing analysis capabilities.

Reliability is a fundamental component of every design flow. For this reason, TSMC and Mentor have developed a stacked die solution based on the Mentor Calibre PERC™ reliability platform for TSMC's InFO and CoWoS flows. This new product handles electrostatic discharge (ESD) analysis between dies.

Suk Lee, Senior Director of Design Infrastructure Marketing at TSMC, said, “Through our collaboration with Mentor, we are helping our joint customers rapidly realize the benefits of using TSMC’s InFO and CoWoS packaging solutions,” adding, “With Mentor’s design suite for TSMC’s InFO and CoWoS, customers in the automotive, networking, high-performance computing (HPC), and numerous other markets can achieve a new level of integration.”

Joe Sawicki, Vice President and General Manager of Mentor’s Design to Silicon business unit, said, “We are honored to be able to further improve and advance Mentor’s design solutions for InFO and CoWoS packaging technologies together with our long-time partner, TSMC,” and added, “Through this collaboration, we have contributed to making 3D-ICs a viable alternative to mainstream 1D IC designs. This is enabling an increasing number of customers to achieve truly amazing innovations that will change the world.”