Lam Research announced a new solution for increasing chip memory density in artificial intelligence and machine learning.

With the introduction of VECTOR® DT for backside deposition and EOS® GS wet etch for backside and bevel film removal, Lam Research expands its global wafer stress management product portfolio.

While high-aspect-ratio (HAR) deposition and etching are key technologies for 3D NAND scaling, increasing the number of deposition layers while controlling wafer bow due to stress accumulation in the stacked thin films has been a major challenge.

Wafer distortion caused by such stresses significantly affects wafer yield by reducing lithography depth-of-focus, degrading overlay performance, and causing structural deformation.

Improving overall yield requires careful management of stress at the wafer, die, and feature levels throughout the entire manufacturing process flow. In some cases, processes that could enhance performance are excluded due to their stress characteristics.

The VECTOR DT system, which provides an economical solution for controlling wafer bow in 3D NAND manufacturing, is the latest addition to Lam Research's plasma-enhanced chemical vapor deposition (PECVD) line.

VECTOR DT is a single-step solution that manages wafer shape by depositing a variable counter-stress film on the back of the wafer without touching the front side. This improves lithography results, reduces bow-induced defects, and enables high-performance, high-stress thin films.

In addition to counter-stress film deposition, Lam Research also offers backside film strip technology to enable customers to flexibly adjust wafer stress during 3D NAND manufacturing, and its EOS GS wet etch product complements the VECTOR DT.

Simultaneously removing backside and bevel films, it achieves industry-leading wet etch uniformity while completely protecting the front side of the wafer. Lam Research's EOS GS, part of its comprehensive wafer bow management solution, is also the product of choice for memory manufacturers worldwide.

“Our customers continue to significantly increase the number of memory cell layers, which can push cumulative stress and wafer bow beyond the limits of lithography equipment,” said Shesha Varadarajan, vice president of product management at Lam Research. “Minimizing stress-induced distortion is key to achieving target yields and realizing our cost-per-bit roadmap.”

“Lam Research is also expanding its stress management solutions to support customers’ vertical scaling roadmaps by adding the VECTOR DT and EOS GS systems to comprehensively manage stress,” he added.