Source Down, New Industry Standard Package Concept
Connect the source potential to the heat pad instead of the drain potential.
R _DS(on) can be reduced by up to 30% compared to current technology


Infineon Technologies announced on the 12th that it has launched the OptiMOS 25V product, the first power MOSFET to apply the new industry standard package concept, 'Source Down'.

OptiMOS 25V MOSFETs provide low on-state resistance (R _DS(on) ) and high thermal management capabilities, making them suitable for various applications such as drives, SMPS, and battery management.

The new package concept connects the source potential to the thermal pad instead of the drain potential. This enables new PCB layouts and helps achieve higher power density and performance.

Infineon offers two footprint versions, source-down standard gate and source-down center gate, in a PQFN 3.3×3.3mm package.

The source-down standard gate version uses the current PQFN 3.3×3.3mm pinout configuration. Since the electrical wiring locations are the same, the standard drain-down package can be directly replaced with a new source-down package.

The center gate version allows multiple MOSFETs to be configured in parallel by moving the gate pin to the center. The drain-source creepage distance is wider, allowing the gates of multiple devices to be connected on a single PCB layer. Additionally, moving the gate to the center increases the source area and improves the electrical connection of the devices.

This technology can reduce R _DS(on) by up to 30% compared to current technology. Junction-to-case thermal resistance (R _thJC ) has also been significantly improved compared to current PQFN packages. By lowering parasitic components, reducing PCB losses, and offering superior thermal performance, it provides advantages for various advanced engineering designs.