November 1, 2012, Seoul — STMicroelectronics (ST), Soitec, and Circuits Multi Projets® (CMP) announced that they are providing ST’s CMOS 28nm FD-SOI process, utilizing Soitec’s innovative silicon substrates, to universities, research institutes, and design firms for prototyping work through CMP’s silicon brokerage services. ST decided to provide the technology to these institutions as the first commercial wafer of this process technology is nearing completion.

Support for ST's 28nm FD-SOI CMOS process via CMP was decided based on the successful partnerships established over the years, during which CMP has supported these universities and design firms with existing CMOS generations, including 45nm (introduced in 2008), 65nm (introduced in 2006), 90nm (introduced in 2004), and 130nm (introduced in 2003). CMP's customers can also access ST's 65nm and 130nm SOI processes, as well as the 130nm SiGe process. In fact, approximately 170 universities and companies have received ST's 90nm CMOS process design methods and design kits, while over 200 have received design methods and design kits for ST's 65nm bulk and SOI CMOS processes.

Since CMP provided ST's 28nm CMOS bulk technology in 2011, more than 60 universities and microelectronics companies have received design methods and design kits, and 16 ICs have already been manufactured.

Bernard Courtois, Director at CMP, stated, “There is very high interest in IC designs applying these process technologies. Over 300 projects have been designed using 90nm (discontinued in 2009), and there are already more than 300 projects using bulk 65nm. In addition, there are already over 60 projects using 65nm SOI.” It should also be noted that many top-tier universities in Europe, the U.S./Canada, and Asia are enjoying these benefits from the collaboration between CMP and ST,” he mentioned.

With the CMP multi-project wafer service, it has become possible to place small orders of advanced ICs ranging from tens to thousands. The cost of the 28nm FD-SOI CMOS process is 18,000 euros per mm², and the minimum order unit is 1 mm².

Philippe Magarshack, Vice President of Design Commercialization and Services at ST, stated, “The first designs utilizing FD-SOI technology are already in progress, making now the right time to offer this technology to research institutions. ST’s FD-SOI manufacturing process allows for the easy and rapid porting of designs to FD-SOI, offering significant advantages in terms of power and performance. Furthermore, universities gaining access to ST’s cutting-edge technology will help recruit top young engineers, aligning with our commitment to maintaining our position as a technology leader in the long run.”

Steve Longoria, Senior Vice President of Global Strategic Business Development at Soitec, stated, “Our partnership with ST and CMP is a prime example of Soitec’s commitment to providing diverse material solutions to the open market. We believe this will enable us to expand the FD-SOI ecosystem and support users of cutting-edge technologies. Through this partnership, we will be able to discover new and innovative products utilizing Soitec’s FD-SOI materials, ultimately providing universities and other customers with a clear path to developing and testing next-generation ICs.”