Cadence Cerebros, with specialized machine learning technology
Productivity up to the system semiconductor sign-off stage
Supports up to 10x and 20% PPA improvement


On the 2nd, Cadence launched the machine learning-based 'Cerebrus™ Intelligent Chip Explorer' tool that supports digital chip design automation and achieving chip design goals. Engineers can quickly identify flow solutions that are difficult to design explore, improving productivity and reducing power consumption by 20% to improve Power Performance Area (PPA).

Cerebus works with Cadence's synthesis solution (Genus™), automated place and route implementation system (Innovus™), timing signoff solution (Tempus™), RTL power solution (Joules™), IC power integrity solution (Voltus™), and physical verification signoff solution (Pegasus™) to provide customers with a path to improved verification and predictability.

The combination of the new product and the Cadence RTL-to-signoff flow will increase the productivity of chip designers, CAD and IP developers by up to 10x compared to traditional manual methods, and help improve power and PPA by up to 20%.

With enhanced machine learning capabilities, Cerebus quickly identifies flow solutions that engineers might not explore, and automatically applies design learnings to future designs, reducing the iteration time required to achieve better results.

Additionally, Cadence Cerebus enables a single engineer to optimize and parallelize the entire RTL-to-GDS flow across multiple design blocks simultaneously, increasing productivity across the entire design team. Additionally, it accelerates flow optimization with a scalable design exploration method that can be used on-premises or in the cloud.

“As we provide the latest semiconductor processes, we place the utmost importance on the efficiency of our Design Technology Co-Optimization (DTCO) program,” said Kim Sang-yoon, senior vice president of Samsung Foundry Design Technology. “We are continuously exploring ways to improve PPA and productivity in chip implementation.”

He continued, "Samsung Foundry has used Cerebus and Cadence digital implementation flows across multiple application products, reducing work that previously took months to complete in just days, and has seen power savings of more than 8% in some of the most critical design blocks." He added that the final design development time has been improved by more than 50%.

“Cerebrus and Cadence Systems’ semiconductor signoff tools will enable a new approach to the development of advanced design projects by increasing design performance by more than 10% through automated flow optimization and floorplan exploration,” said Satoshi Shibatani, Digital Design Director, EDA Division, Renesas Shared R&D.

“As the industry continues to move to more advanced processes, design complexity is increasing,” said Chin-Chi Teng, Senior Vice President and General Manager of Cadence Digital & Signoff Group. “Cerebrus is the solution that efficiently achieves PPA goals.”