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Up to 30 percent reduction in RDS(on) compared to the latest drain-down packages.
A power MOSFET is being launched that reduces package losses that limit the overall performance of the device and reduces space at the system level by approximately 65 percent.
Infineon Technologies (Korea CEO Seung-Soo Lee) announced on the 11th that it is launching the next-generation OptiMOS™ Source-Down power MOSFET.
These products are available in a PQFN 3.3mm x 3.3mm package and in various voltage ranges from 25V to 100V.
Setting a new standard in MOSFET performance, this package delivers higher efficiency, power density, superior thermal management and a lower bill of materials.
It is suitable for applications such as motor drives, SMPS for servers and telecom, OR-ing and battery management systems.
Compared to the standard drain-down concept, the latest source-down packaging technology allows for a wider silicon die to fit within the same package outline.
By reducing package losses that limit the overall performance of the device, RDS(on) can be reduced by up to 30 percent compared to the latest drain-down packages.
At the system level, the SuperSO8 5mm x 6mm footprint is PQFN 3.Replacing the 3mm x 3.3mm package allows for a space reduction of approximately 65 percent, enabling a smaller form factor.
By effectively utilizing the remaining space, the power density and system efficiency of the final system can be increased.
Additionally, the source-down concept dissipates heat directly to the PCB through thermal pads instead of bond wires or copper clips.
This simplifies thermal management by improving the thermal resistance RthJC by more than 20 percent from 1.8K/W to 1.4K/W.
Infineon offers two footprint versions and layout options: source-down standard gate and source-down center gate.
The standard gate layout simplifies drop-in replacement for drain-down packages, and the center-gate layout facilitates parallelization.
These two options provide optimal device placement on the PCB, optimization of PCB parasitics, and ease of use.
Infineon Technologies (Korea CEO Seung-Soo Lee) announced on the 11th that it is launching the next-generation OptiMOS™ Source-Down power MOSFET.
These products are available in a PQFN 3.3mm x 3.3mm package and in various voltage ranges from 25V to 100V.
Setting a new standard in MOSFET performance, this package delivers higher efficiency, power density, superior thermal management and a lower bill of materials.
It is suitable for applications such as motor drives, SMPS for servers and telecom, OR-ing and battery management systems.
Compared to the standard drain-down concept, the latest source-down packaging technology allows for a wider silicon die to fit within the same package outline.
By reducing package losses that limit the overall performance of the device, RDS(on) can be reduced by up to 30 percent compared to the latest drain-down packages.
At the system level, the SuperSO8 5mm x 6mm footprint is PQFN 3.Replacing the 3mm x 3.3mm package allows for a space reduction of approximately 65 percent, enabling a smaller form factor.
By effectively utilizing the remaining space, the power density and system efficiency of the final system can be increased.
Additionally, the source-down concept dissipates heat directly to the PCB through thermal pads instead of bond wires or copper clips.
This simplifies thermal management by improving the thermal resistance RthJC by more than 20 percent from 1.8K/W to 1.4K/W.
Infineon offers two footprint versions and layout options: source-down standard gate and source-down center gate.
The standard gate layout simplifies drop-in replacement for drain-down packages, and the center-gate layout facilitates parallelization.
These two options provide optimal device placement on the PCB, optimization of PCB parasitics, and ease of use.
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