[Editor's Note] When people think of semiconductors, they usually think of familiar semiconductors like computer CPUs and memory. Conversely, MCUs (Micro Controller Units), the core semiconductors that power electronic devices, are widely used in virtually every electronic device we encounter, yet they remain relatively unfamiliar to the general public. Recently, MCUs have been making headlines due to the semiconductor shortage, drawing public attention. Therefore, this magazine has prepared a series of articles by Yuji Kawano, Manager at STMicroelectronics, a company specializing in MCU semiconductors, to provide an in-depth look at MCUs.

■ MOS manufacturing on silicon wafers is important

The MCU manufacturing process involves several steps. Each MCU consists of numerous MOS transistors. MOS transistors are more accurately called MOSFETs (metal oxide semiconductor field effect transistors), but will be simply referred to as MOS in this article. A crucial part of the MOS manufacturing process is the fabrication of MOS transistors on silicon (symbol: Si) wafers. This article will examine the various processes involved in MCU production. Knowledge of these processes is essential for engineers who use MCUs.

■ Upstream and downstream processes
MCU customers are also paying close attention to MCU manufacturing plants, as recent large-scale disasters (e.g., earthquakes) have damaged upstream and downstream factories of major MCU manufacturers, disrupting product supply chains.

To ensure supply stability from major natural disasters like these, STMicroelectronics (hereafter referred to as ST) has a policy of manufacturing products in two or more factories on different continents. Upstream processes are assigned to two or more factories, and downstream processes are assigned to two or more other factories. This arrangement is intended to prevent disruption of ST's MCU supply even if one of its factories is damaged by a major natural disaster.





What does length mean in MCU process designations?

You may see terms like "180nm CMOS process" or "90nm process" in MCU catalogs, manuals, or new product articles. You may also have heard of "microfabrication process" or "process miniaturization." What do these terms mean?

If you have any knowledge of semiconductors, you'll know that decreasing numbers like 180nm and 90nm indicate miniaturization, with smaller numbers indicating more advanced processes. But what do these numbers mean for MCUs?

These numbers represent the size of the shortest (minimum) part of the micromachined wafer area. This refers to the "minimum feature size" of the process. But more specifically, what part is the shortest distance?

Different MCU manufacturers use different processes for their minimum feature sizes. For example, if the metal wiring film width is the shortest, that width is the minimum outline size, and if the MOS gate length is the shortest, that length is the minimum outline size. In most cases, the MOS gate length is the minimum outline size.




Figure 2 is a cross-sectional view of a MOS. The length between the drain and source is the gate length (L). The size of the other side of the gate is the gate width (W).

Gate length affects MOS switching speed, current passing between drain and source, gate capacitance, etc. For this reason, the L value is commonly used in process designations.

The 180nm CMOS process has a MOS gate length of 180nm. The MOS gate has the shortest length in the CMOS structure. The reduction in MOS size (such as L = 90 nm) is called process shrink.

For ST's MCUs, the STM32F103 series is manufactured using a 180nm CMOS process, and the STM32F429 series is manufactured using a 90nm CMOS process.

What is CMOS?





In MCU process designations, the minimum external size is followed by CMOS, which stands for "complementary MOS." CMOS is a transistor with a gate structure consisting of p-channel MOSFETs and n-channel MOSFETs in a complementary arrangement. A p-channel MOS (also called a PMOS) turns off when a voltage is applied to its gate, and an n-channel MOS (also called a nmOS) turns on when a voltage is applied to its gate. Figure 3 illustrates an inverter circuit (logical NOT operator) composed of CMOS, nmOS, and PMOS circuits.

NMOS and PMOS circuits consume relatively large amounts of energy because direct current flows through the resistor and MOS when the MOS is turned on. However, since one of the MOS transistors is (theoretically) always turned off, no direct current flows through the CMOS circuit, resulting in low power consumption. Almost all MCUs today have a CMOS structure.

■ Process refinement lowers overall costs





Because each wafer is sheet-processed on an MCU production line, the cost per wafer remains the same regardless of the number of MCUs on the wafer. Therefore, manufacturing as many MCUs as possible on a wafer reduces costs. Figure 4(a) is a diagram illustrating this. However, in practice, this simple calculation method cannot be used to determine costs. Process scaling increases the costs of photomasks and production lines. Furthermore, because the bonding pads that connect leads to dies (chips) have a fixed mechanical size, the die (chip) size cannot be infinitely reduced along with the MOS size. However, the diagram demonstrates that, generally speaking, process scaling tends to lower overall costs.





As shown in Figure 4(b), high-speed circuits can be fabricated by increasing the MOS switching speed through microfabrication. However, as shown in Figure 4(c), a relatively large leakage current occurs when the circuit is OFF, increasing the MCU standby current. Furthermore, microcircuits are easily influenced by external signals, making them vulnerable to noise.

This means that process miniaturization has both advantages and disadvantages. However, thanks to development engineers who compensate for the disadvantages and maximize the advantages, today's microprocessed MCUs boast low standby current and high noise resistance.