Xilinx Korea (Division President Ahn Heung-sik) December 11, 2013 – Xilinx announced product documentation and Vivado® Design Suite support accompanying the launch of its 20nm All Programmable UltraScale™ portfolio. Xilinx maintained aggressive momentum toward UltraScale device launch, delivering its first 20nm silicon in early November this year. This device represents the industry's only ASIC-class programmable architecture combined with Vivado ASIC-strength design suite and UltraFast™ design methodologies, delivering ASIC-class capabilities.

This new Xilinx® UltraScale product portfolio, based on UltraScale architecture and TSMC's 20SoC process with exceptional gate density, extends the breadth of Xilinx's market-leading Kintex® and Virtex® FPGA and 3D IC product families. UltraScale devices enable 1.5 to 2x perceived system performance and integration while consuming only half the power of presently available solutions. Through next-generation routing, ASIC-like clocking, and improvements in logic and fabric, these devices eliminate interconnect bottlenecks while achieving sustained device utilization above 90% without performance degradation.

Moshe Gavrielov, Xilinx President and CEO, stated, "Xilinx continues to lead in enabling the fastest time to market through technological innovation and breakthrough products." He added, "UltraScale devices combine Xilinx's UltraScale ASIC-class architecture with Vivado ASIC-strength design suite and UltraScale methodologies to deliver ASIC-class capabilities to our customers. This combination of silicon and design solutions enables customers to achieve meaningful system differentiation fastest and provides a far superior alternative to ASIC and ASSP approaches."

Dr. Mark Liu, TSMC President and Co-CEO, stated, "Through our collaboration with Xilinx, numerous new technologies and methodologies have been developed and deployed." He added, "With the emergence of the first 20nm UltraScale architecture products, Xilinx and TSMC demonstrate how synergy between silicon process and device architecture maximizes product performance and achieves optimal system value."