Nepes (CEO Lee Byeong-gu), a leading semiconductor post-processing foundry company, has secured high-density, ultra-thin 3D packaging technology applicable to the production of high-performance artificial intelligence semiconductors, taking a step ahead in the competitiveness of its advanced post-processing platform.

On the 12th, Nepes announced that it had completed the development of 'key materials and process technology for 3D IC manufacturing using FOWLP', a 3D integrated packaging technology, key materials, and test solution applicable to high-performance artificial intelligence semiconductors, together with a joint research group.

The project was led by Nepass and was carried out for approximately five years starting in 2018.

In particular, this research was initiated with the participation of a consortium of numerous organizations, including Microfriend, Chemi, Korea Electronics Technology Institute, Seoul Technopark, Korea Institute of Materials Science, Seoul National University of Science and Technology, and Deoksan Hi-Metal, with the goal of securing the advancement of the Korean semiconductor industry and the competitiveness of advanced post-processing platforms through the development of advanced semiconductor core technologies.

FOWLP (Fan-Out Wafer Level Packaging) is an advanced packaging technology that can integrate multiple chips into a single package. Breaking away from the traditional method of cutting dies and placing them on a substrate to connect them to contact points, it forms electrodes directly on the wafer and packages multiple dies simultaneously.

Since Infineon first successfully implemented it in 2010, it has been used by advanced semiconductor companies such as TSMC.

The main technologies developed in the national project include: △Fan-out based high-density heterogeneous stacking technology, △Large-area EMI shielding and heat dissipation EMC molding package technology, △PSPI polymerization and low-temperature curing insulating film photosensitive material, and △Development of probe cards for fine pitch response.

Based on these technologies, customers can achieve high-density 3D packages with miniaturization and thinning of form factors and excellent heat dissipation and electrical characteristics. It is expected that the use of fan-out technology-based heterojunction technology and large-capacity interface technology will enable the realization of core technologies in areas such as artificial intelligence semiconductors, edge computing, and cloud servers.

Although Korea is a global leader in the memory industry, its influence in the non-memory market, which is more than twice as large, is minimal, with a share of less than 3%.

There are growing voices calling for South Korea to establish a strategy that focuses on securing advanced packaging technology, a key semiconductor process, and fostering a semiconductor industry ecosystem if it is to become a true semiconductor powerhouse.

Accordingly, the research team focused on semiconductor packaging process and material technology to realize the intelligence, low power consumption, weight reduction, and miniaturization of high-performance semiconductors, for which demand is rapidly increasing across application industries such as AI, robotics, and IoT.

Nepes plans to use the package competitiveness it has secured through this project to explore commercialization opportunities with domestic and international artificial intelligence and memory demand companies.

Kim Jong-heon, Vice President of the Technology Development Division, said, “We expect that this national project will contribute to the expansion of new markets in the advanced semiconductor field,” and “Going forward, Nepes plans to lead advanced post-processing technology and further solidify the foundation of the domestic industrial ecosystem.”