Xilinx, which has been promoting the transition from programmable logic devices to All-Programmable, has newly launched its 16nm UltraScale+ product family comprising FPGA, 3D IC, and MPSoC. Building on the success of the 20nm UltraScale product family, this product family combines new UltraRAM memory, 3D-on-3D, and multi-processing SoC (MPSoC) technology, and incorporates SmartConnect, a new interconnect optimization technology, further enhancing performance and integration. These devices expand Xilinx's UltraScale portfolio while including 20nm and 16nm FPGA, SoC, and 3D IC devices, and by adopting TSMC's 16nm FF+ 3D transistors, significantly increases performance per watt. Regarding some details related to the presentation content of this UltraScale+ product family as well as future challenges and the markets on which Xilinx is currently focused, we spoke with Vincent Tong, Senior Vice President of Global Operations and Quality at Xilinx.

e4ds: With Power Islands for power scalability, is adjustment done only once when leaving the factory, or can it continue to be adjusted afterwards?

Vincent Tong: Adjustment is not limited to a single time; everything is reconfigurable. You can shut down entire blocks, and depending on performance requirements, you can apply somewhat different voltages.

e4ds: You mentioned that SmartConnect realizes various performance and power benefits, but doesn't the process of connecting so smartly result in drawbacks such as speed delays?

Vincent Tong: No, that does not happen. This is a very smart intelligent algorithm that identifies which paths are important in terms of speed and interconnects them appropriately, while placing other less critical paths in different parts of the interconnect. Typically, system performance depends on just one or two critical paths. Therefore, it is designed so that by handling these critical paths first and then handling other paths that have less impact on performance, system performance is not degraded.

e4ds: In 3D-on-3D, when you interpose a 3D IC on FinFET, are there currently 3 layers being stacked?

Vincent Tong: Basically, it is 3D transistors stacked on top of a 3D package. Therefore, it is actually 2 layers, not 3 layers.

e4ds: What is the potential development capacity of this layer stacking in terms of, for example, improved integration density?

Vincent Tong: There are issues with stacking higher. The reason we stack only 2 layers is because of thermal issues. Heat dissipation is a very delicate matter. The top layer has all the active circuits, while the silicon at the bottom has no active circuits. They are all metal interconnects. Since these do not consume power, there is no heat generation issue. However, if we continue stacking active circuit layers, thermal issues will inevitably occur. That is why we are currently stacking only 2 layers.

e4ds: In other words, there are limitations to stacking.

Vincent Tong: Yes, the main reason for the limitation is the thermal issue. Silicon has heat sinks that can help dissipate heat from the silicon. However, if we continue stacking silicon, where would the heat from the silicon in the middle go? If heat dissipation does not occur, it will become extremely hot. When that happens, performance degradation is inevitable, and ultimately thermal runaway will occur and destroy the device.

e4ds: Would you need to immerse the chip in liquid nitrogen? :)

Vincent Tong: That would only cover the surroundings. The chip in the middle of the stack would still have issues. Therefore, this issue must be handled very carefully.

e4ds: What is Xilinx's next focus?

Vincent Tong: I believe Xilinx's most important next step is software-defined, or SD. Let's say we have very complex silicon. The problem is that only FPGA users or ARM users know how to use it. However, beyond these, there are many software engineers. Therefore, what we need to do to expand our market is to provide tools that attract software engineers, not to create more complex silicon. Of course, we must continuously add functions to the silicon, but we must also explore how to attract more users to FPGA. This is a very important issue.

e4ds: In other words, it's like what Steve Jobs did with the iPhone?

Vincent Tong: Yes. Exactly. This is a platform. When you create a platform, don't people write apps for it? Those who write apps for iPhone don't need to know how iPhone works. At least not every detail. Yet they can still write apps. It's the same for Xilinx. Here, there's a chip. Can you use it? Of course not. Because you're not an FPGA developer. But if you're a software engineer, you can write applications for it. The situation becomes much better. In fact, this is Xilinx's greatest focus. The reduction of silicon nodes will continue to progress with 16 nanometers, 10 nanometers, and so on. But this is also why software-defined, or SD, is so important at the same time. It allows more software engineers to use it. This is a very important matter and is the very concept of our efforts.

e4ds: Yes, I understand well. Thank you.