An ultra-small, low-power circuit technology has been developed that minimizes reference spurs in clock signals, which determine the high-speed operation of semiconductor chips. The technology has been numerically demonstrated to deliver high-quality clock signals, a requirement for high-speed processing of large amounts of data, such as 5G and 6G communication chips and AI chips.

A research team led by Professor Hee-In Yoon of the Department of Electrical and Electronic Engineering at UNIST announced on the 11th that they have developed a semiconductor circuit for generating clock signals based on an ILCM (Injection-Locked Clock Multiplier) that significantly reduces noise. The results of the research were published in the February 6th issue of the IEEE Journal of Solid-State Circuits, an academic journal in the field of semiconductor circuits.

■ Application of reference spur suppression design

Semiconductor chips operate in response to a clock, a periodic electrical signal. In high-speed communications and AI computing environments, noise characteristics of the clock signal, such as jitter and reference spurs, directly impact system performance. Although the ILCM method is advantageous in reducing jitter, it has a limitation in that reference spurs occur during the reference signal injection process.
The research team adopted a ring oscillator (Ring VCO)-based ILCM structure and applied frequency tracking (SSFTL) and reference signal injection timing compensation (IPTC) designs to minimize reference spurs.

■ -81.36dBc at 2.1GHz·Jitter 280.9fs

The developed circuit achieved a reference spur of –81.36 dBc at 2.1 GHz output, the lowest level among reported ring oscillator-based ILCM circuits. Jitter was also reduced to 280.9 femtoseconds (fs).

Based on the 28nm CMOS process, the circuit area is 0.0444mm² and power consumption is 12.28mW, achieving both integration and power efficiency. The research team explained that the technology can be utilized in 6G communications, AI chips, and clock sources for high-speed interconnects.

This study was conducted with the support of the "Regional Intelligence Innovation Talent Development Project" from the Ministry of Science and ICT, the Semiconductor Design Education Center (IDEC), and the Institute for Information and Communications Technology Planning and Evaluation (IITP).