In all programmable FPGAs, SoCs, and MPSoCs
Rapid wireless system development and implementation

Xilinx announced the release of System Generator 2015.3 for DSPs. This release is a tool for designing DSP systems using Xilinx All Programmable Devices. Developers can implement product-quality DSPs faster than with traditional RTL within a ^MATLAB® and ^Simulink® model-based environment. By combining new blocksets with faster simulation and editing runtimes, it enables a higher level of design abstraction and 7x improved design generation for wireless algorithm development.

In this new release, HDL Coders enable high-level design abstraction by complementing the system generator block scheme for the ^Vivado® design suite. This allows high-level and target-optimized code, which is fluidly mixed, to achieve optimal implementation results. In addition, this new flow implements reusable data paths within the system generator, enabling easy connection of System-on-Chip (SoC) platforms containing JESD204 and CPRI interfaces, as well as wireless radio IP such as CFR (crest factor reduction).

Jim Tung, a principal researcher at Mathworks, stated, “Mathworks continues to extend code generation, verification, and platform support capabilities targeting wireless radio algorithms to Xilinx FPGAs and All Programmable SoCs,” adding, “The enhanced system generator can be used in conjunction with the HDL coder to enable faster prototyping and IP generation for Vivado IP integration. Additionally, by simulating advanced behavior algorithms and optimized IP in Simulink, our customers can significantly shorten time-to-market.”

Verification and editing 7 times faster with enhanced blocksets

The system generator blockset for digital up converters and digital down converters (DUC/DDC) significantly simplifies wireless algorithm development. Improvements to the verification and compilation runtime have been added to the new block, and it consists of seven or fewer parameters.

Digital FIR filter blocks are integrated with MathWorks' filter design and analysis tools to create efficient filter regions, including fixed-fractional interpolation and decimation types. This allows sine wave and complex product blocks to significantly simplify modulator design for frequency conversion at high sample rates. Additionally, requantize blocks enable rapid manipulation of data types, maximizing dynamic range at any point in the data path.