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(Xilinx website video - 56G PAM4 Technology capture)
Realizing New Ethernet Advancements with 400G Density and Terabit Interfaces
Xilinx announced that it has developed a 16nm FinFET+-based programmable device implementing 56G transceiver technology using a four-stage Pulse Amplitude Modulation (PAM4) transmission scheme. The PAM4 solution doubles the bandwidth of existing infrastructure to support new Ethernet deployments for optical and copper interconnects. Xilinx stated that it is introducing and showcasing innovative 56G technologies ahead of PAM4's mass adoption, helping to educate suppliers and ecosystem members and prepare for the changes.
Ken Chang, Vice President of Xilinx’s SerDes Technology Group, said, “Xilinx customers are already anticipating how to accelerate next-generation applications.” "Xilinx aims to raise awareness of 56G PAM4 technology solutions to help customers prepare for design changes," said Xilinx, adding, "We are pleased to be able to showcase our technology."
As trends such as cloud computing, the Industrial Internet of Things (IIoT), and Software-Defined Networks (SDN) increase and drive the need for infinite bandwidth, technological innovation must not only expand 50G, 100G, and 400G ports but also maximize port density with terabit interfaces without increasing costs or power per bit. Standardized next-generation line rates are paramount in meeting these ongoing bandwidth requirements.
Xilinx is leading the standardization of 56G PAM4 at both the Optical Internetworking Forum (OIE) and the Institute of Electrical and Electronics Engineers (IEIE). Xilinx's 56G PAM4 transceiver technology was developed to overcome the physical limitations of existing data transmission at line rates, including insertion loss and crosstalk. It supports copper and optical interconnects in chip-to-chip, module, direct-attach cable, and backplane applications. Furthermore, it enables next-generation system designs extending beyond terabit line cards to 400G-to-terabit chassis backplanes.
Sajiv Dalal, TSMC North America Vice President, stated, “TSMC is preparing PAM4 devices for 16nm FinFET+ in collaboration with Xilinx,” adding, “This innovative transceiver is the result of our long-standing collaboration with Xilinx.” "TSMC is committed to high-performance computing and looks forward to Xilinx's leading technology demonstration later this month," he added.
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