ESD protection device of 0.13μm process for analog power semiconductors

Toshiba Corporation has developed an electrostatic discharge (ESD) protection device for analog power semiconductor applications.

This device is manufactured using advanced 0.13μm process technology, optimizing the transistor structure and significantly improving ESD characteristics. ESD protection capabilities have increased by up to four times, making it much more robust, and the standard deviation is only one-twelfth of that of existing devices.

Toshiba identified a transistor structure optimization mechanism that enables ESD strength through 3D simulation analysis. Toshiba announced these findings at the “ISPSD2016” international semiconductor symposium held in the Czech Republic on June 14, 2016.

Since ESD current flow raises the local temperature inside silicon, semiconductor devices can be destroyed if an ESD surge is introduced from the human body or equipment. ESD protection devices must protect internal circuits, which is especially true for analog power semiconductor devices that require high rated voltages ranging from 10V to 100V.

In this case, the ESD protection device must secure a high current flow, which results in an increase in chip size. The reduction in size of ESD protection devices is linked to the problem of implementing more compact chips.

Toshiba used 3D simulation analysis of ESD to reveal that ESD-induced destruction occurs due to a rise in lattice temperature caused by current flow at the peak of the electric field.

By modifying the transistor structure to extend the low-resistance drain region toward the source and suppress silicon lateral resistance, current flow is diverted from the bottom of the drain toward the source and isolated at the peak of the electric field. It was found that this optimized design increases ESD strength by up to four times and reduces the standard deviation to one-twelfth. Additionally, the device size requiring HBM ±2000V was reduced by 68%.

Toshiba offers an advanced analog process platform utilizing 0.13μm process technology, which can be embedded in passive devices such as resistors and capacitors, as well as CMOS, DMOS, and bipolar transistors. Users can select the process suitable for each application from the following three process platforms: the “BiCD-0.13” (DMOS lineup up to 100V), primarily used in automotive applications; the “CD-0.13BL” (DMOS lineup up to 60V), primarily used in motor drivers; and the “CD-0.13” (DMOS lineup up to 40V), primarily used in power management ICs.

Toshiba plans to launch products using the CD-0.13 process with this technology applied in 2017 and continue to implement other process platforms to improve electrostatic discharge characteristics.