Xilinx has launched the Virtex®-7 HT FPGA, featuring 28Gbps serial transceiver performance required for next-generation 100-400Gbps applications. This 28nm FPGA enables telecommunications equipment operators to develop integrated high-bandwidth efficiency systems to meet the massive global demand for higher bandwidth efficiency in wired infrastructure and data centers. To support stringent optical and backplane protocols, this new device is equipped with serial transceivers that offer the industry's highest speed and lowest jitter among FPGA serial transceivers.

Joseph Byrne, Senior Analyst at Linley Group, stated, “Industry forecasts that current 15 exabytes per month will approach 64 exabytes per month highlight the need for higher bandwidth system-on-chip solutions capable of operating high-speed signals with excellent signal integrity and low power efficiency for deployment in fiber-optic infrastructure and other existing infrastructures.” He added, “As the telecommunications industry increases interface speeds from 10 Gbps to 100 Gbps to provide greater capacity, requirements for chip-to-optic, chip-to-backplane, and chip-to-chip interfaces have also become very stringent. Therefore, in providing 28 Gbps transceivers with the Virtex-7 HT device, Xilinx has focused primarily on balancing integration with constraints on power, performance, and optical jitter.”

The Virtex-7 HT device, built with 4 to 16 28Gbps transceivers conforming to the OIF CEI (Optical Internetworking Forum's Common Electrical I/O)-28G standard, is designed to connect to next-generation CFP2 and QSFP2 optical modules used in next-generation 100-400Gbps system line cards. Additionally, this device can provide up to 2.8Tbps full-duplex throughput with up to 72 13.1Gbps transceivers. This enhances the overall system performance of the Virtex-7 family with twice the logic capacity, 1.3 times greater memory bandwidth, twice the static power efficiency, and 2.7 times higher bandwidth than competing devices.

In a newly posted video on the Xilinx website ( www.xilinx.com ), signal integrity expert Dr. Howard Johnson demonstrates the 28Gbps serial transceiver on the Virtex-7 HT FPGA. Using a real PRBS31 pattern, this demo highlights the wide open eye and jitter performance required for interfacing with next-generation CFP2 optics. (Watch video: http://www.xilinx.com/technology/videos.htm )

Christian Urricariet, Marketing Director for High-Speed Optical Devices at Finisar, stated, “To meet increasing market demand for bandwidth, telecommunications equipment operators will design next-generation 100 and 400Gbps systems utilizing next-generation CFP/2 optical module form factors. This maximizes faceplate bandwidth density while improving the power dissipation budget of existing form factors.” He added, “Through our collaboration, Xilinx has introduced a simple, low-jitter single-chip solution that enables higher port densities by providing a direct 28Gbps connection between the FPGA and the CFP/2 module.”

Through the feature mix of this device, from a low-cost 100G “smart gearbox” chip with 290,000 logic cells to 870,000 logic cells